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Influence of Pre-Gate Cleaning ON Si/SiO2 Interface and Electrical Performance of Cmos Gate Oxide

Published online by Cambridge University Press:  21 March 2011

X. Duan ,
K. Kisslinger ,
L. Mayes ,
S. Ruby  and
J. Barrett
X. Duan
Affiliation:
National Semiconductor Corp., South Portland, ME 04106 MIT, Dept. of Materials Science and Engineering, Cambridge, MA 02139
K. Kisslinger
Affiliation:
National Semiconductor Corp., South Portland, ME 04106
L. Mayes
Affiliation:
National Semiconductor Corp., South Portland, ME 04106
S. Ruby
Affiliation:
National Semiconductor Corp., South Portland, ME 04106
J. Barrett
Affiliation:
National Semiconductor Corp., South Portland, ME 04106
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Abstract

The Si/SiO2 interface is attracting new interest as gate dielectrics in MOS devices become ultra thin. In this paper, the impact of pre-gate cleaning on the morphology of the Si/SiO2 interface and the electrical performance of CMOS gate oxides has been systematically investigated. Using the High-Resolution Transmission Electron Microscopy (HRTEM) technique, we observed the Si/SiO2 interface at an atomic level. We have found a direct experimental relationship between the pre-gate cleaning scheme, Si/SiO2 interface morphology, and the electrical properties of CMOS gate oxides. When the ratio of H2O2:NH4OH ≥ 1.45, the roughness of the Si/SiO2 interface was dramatically improved, which, in turn, increased the Charge-to-Breakdown to an ideal value.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 654: Symposia AA – Structure-Property Relationships of Oxide Surfaces & Interfaces , 2000 , AA3.43.1
Copyright
Copyright © Materials Research Society 2001

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