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High Density Direct Bond Interconnect (DBI) Technology for Three Dimensional Integrated Circuit Applications

Published online by Cambridge University Press:  26 February 2011

Paul Enquist
Paul Enquist*
Affiliation:
[email protected], Ziptronix, Inc., R&D, 800 Perimeter Park, Suite B, Morrisville, NC, 27560, United States, (919) 459-2456
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Abstract

A novel direct wafer bonding technology capable of forming a very high density of electrical interconnections across the bond interface integral to the bond process is described. Results presented include an 8 um interconnection pitch, die-to-wafer and wafer-to-wafer bonding formats, temperature cycling reliability × 10 greater than the JEDEC requirement, connection yield ∼ 99.999, > 50% part yield on parts with ∼ 450,000 connections, and < 0.1 Ohm connection resistance at 1pA without requiring a voltage surge to induce current.

Keywords

bondingCMPsurface chemistry
Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 970: Symposium Y – Enabling Technologies for 3-D Integration , 2006 , 0970-Y01-04
Copyright
Copyright © Materials Research Society 2007

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References

REFERENCES

1. International Technology Roadmap for Semiconductors, 2005 Edition.Google Scholar
2. Lu, J. Q. et. al., “A wafer Level 3D Technology Platform using Dielectric Bonding Glues and Copper Damascene Patterned Inter-Wafer Interconnects”, Proceed. IEEE Int. Interconnect Technology Conf (IITC), 2002, p. 78.Google Scholar
3. Lu, J.Q. et. al., “Evaluation Procedures for Wafer Bonding and Thinning of Interconnect Test Structures for 3D ICs”, Proceed. Int. IEEE Interconnect Technology Conf (IITC), 2003, p. 74.Google Scholar
4. Pozder, S., Lu, J.Q., Kwon, Y., Zollner, S., Yu, J., McMahon, J.J., Cale, T.S., Yu, K., Gutmann, R.J., “Back End Compatibility of Bonding and Thinning Process for a Wafer Level 3D Interconnect Technology Platform”, Proceed. IEEE Int. Interconnect Technology Conf (IITC), 2004, p. 102.Google Scholar
5. Lu, J. Q., Kwon, Y., Kraft, R., Gutmann, R, McDonald, J., Cale, T., “Stacked chip-to-chip Interconnections Using Wafer Bonding Technology with Dielectric Bond Glues”, Proceed. IEEE Int. Interconnect Technology Conf (IITC), 2001, p. 219.Google Scholar
6. Gutmann, R., Lu, J.Q., Kwon, Y., McDonald, J., Cale, T., “3D ICs: A technology Platform for Integrated Systems and Opportunities for New Polymeric Adhesives”, Proceed. IEEE Int. Interconnect Technology Conf (IITC), 2001, p. 173.Google Scholar
7. Burns, J., Warner, K., Gouker, P., “Characterization of Fully Depleted SOI Transistors after removal of the Silicon Substrate”, Proceed. IEEE Int. SOI Conf, 2001, 113.Google Scholar
8. Warner, K. et. al, “Wiring Requirements and 3D Integration Technology for Field Programmable Gate Arrays”, IEEE Trans VLSI, Vol. 11, 2003, p. 44.Google Scholar
9. Burkett, S., Craigle, C., Qiao, X., Temple, D., Stoner, B., McGwire, G., “Processing Techniques for 3D Integration”, Superficies y Vacio, V. 13, 2001, p. 1.Google Scholar
10. Stoner, B., Temple, D., “Vertical Interconnects for 3D Microelectronics Integration”, DARPA 3DMI Workshop, San Diego, 2002.Google Scholar
11. Morrow, P. et. al., “Wafer Level 3D Interconnects Via Cu Bonding”, Adv. Metals Conf, 2004.Google Scholar
12. Klumpp, R. Merkel, Weiland, R., Ramm, P., “Chip to Wafer Stacking Technology for 3D Integration”, Proceed. IEEE Elect. Component Tech Conf, 2003, p. 1080.Google Scholar
13. Ramm, P., Bonfert, D., Gieser, H., Haufe, J., Iberl, F., Klumpp, A., Kux, A., Wieland, R., “Interchip Via Technology for Vertical System Integration”, IEEE Int Interconnect Tech Conf., 2001, 160.Google Scholar
14. Takahashi, et. al., “Development of Advanced 3D Chip Stacking Technology with Ultrafine Interconnectoin”, Proceed IEEE Elect Component Tech Conf, 2001, p. 541.Google Scholar
15. Sunohara, M. et. al., “Development of Wafer Thinning and Double Sided Bump Technology for 3D Stacked LSI”, Proceed IEEE Elect Component Tech Conf, 2002, p. 238.Google Scholar
16. Takahashi, K. et. al., “Current Status of R”, Jpn, J. Applied Physics, Vol. 40, 2001, p. 3032.Google Scholar
17. Takahashi, K. et. al., “Thermal Characterization of Bare die Stacked Modules with Cu through vias”, Proceed IEEE Elect component Tech Conf, 2001, p. 730.Google Scholar
18. Takahashi, K. et. al., “Advanced Packaging Technologies on 3D Stacked LSI Utilizing Micro Interconnections and Layered Microthin Encapsulaton”, Proceed IEEE Elect Component Tech Conf, 2001, p. 353.Google Scholar
19. Tomisaka, M. et. al., “Electroplating Copper Fillings for Through Vias for 3D Chipo Stacking”, Proceed IEEE Elect Component Tech Conf, 2002, p. 1432.Google Scholar
20. Tanaka, N. et. al., “Mechanical Effects of Copper Through Vias in a 3D Die Stacked Module”, Proceed IEEE Elect Component Tech Conf, 2002, p. 473.Google Scholar
21. Umemoto, M., et. al., “Superfine Flip Chip Interconnection in 20 um Pitch Utilizing Reliable Microthin Underfill Technology for 3D Stacked LSI”, Proceed IEEE Elect Component Tech Conf, 2002, p. 1454.Google Scholar
22. Tanida, K. et. al., “Ultra High Density 3D Chip Stacking Technology”, Proceed IEEE Elect Component Tech Conf, 2003, p. 1084.Google Scholar
23. Takahashi, K. et. al., “Process Integration of 3D Chip Stack with Vertical Interconnection” Proceed IEEE Elect Component Tech Conf, 2004, p. 601.Google Scholar
24. Umemoto, M. et. al., “High Performance Vertical Interconnectoin for Hihg Density 3D Chip Stacking Package”, Proceed IEEE Elect Component Tech Conf, 2004, p. 616.Google Scholar
25. Takahashi, K., “Development of 3D Chp Stacking Technology by Si Through-via”, Proceed IMAPS, 2004.Google Scholar
26. Trezza, J., “Multi-Material System on Chip MM-SoC”, 3D Architectures for Semiconductor Integration and Packaging Conference, Burlingame CA, November 2006.Google Scholar
27. Patti, R., “The Design and Architecture of 3D Memory Devices”, 3D Architectures for Semiconductor Integration and Packaging Conference, Burlingame CA, April 2004.Google Scholar
28. Guarini, K. et. al., “Electrical Integrity of State of the Art 0.13 um SOI CMOS Devices and Circuits Transferred for 3D Integrated Circuit Fabrication”, Proceed IEEE IEDM, 2002, p. 943.Google Scholar
29. Moore, G. E., “Cramming more components onto integrated circuits”, Electronics, Volume 38, Number 8, April 19, 1965.Google Scholar
30. Tong, Q.-Y. and Gosele, U., Semiconductor Wafer Bonding, Wiley (1999).Google Scholar
31. Abbott, B. P., Chocola, J., Naumenko, N. and Caron, J.: 2nd Int. Symp. On Acoustic Wave Devices for Future Mobile Comm., Chiba, JP, 2004.Google Scholar
32. US patent 6,902,987, June 7, 2005.Google Scholar
33. Ziptronix web site, www.ziptronix.comGoogle Scholar
34. Enquist, P., “Room Temperature Direct Wafer Bonding for Three Dimensional Integrated Sensors”, Sensors and Materials, Vol. 17, No. 6 (2005), p. 307.Google Scholar
35. Tong, Q. Y., “Room Temperature Metal Direct Bonding”, Applied Physics Letters, 89, 1 (2006).Google Scholar