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From planar to vertical nanowires field-effect transistors

Published online by Cambridge University Press:  13 August 2012

Guillaume Rosaz ,
Bassem Salem ,
Nicolas Pauc ,
Pascal Gentile ,
Priyanka Periwal ,
Alexis Potié ,
Thierry Baron ,
L. Latu-Romain  and
S. David
Guillaume Rosaz
Affiliation:
Laboratoire des Technologies de la Microélectronique (LTM) – UMR 5129 CNRS-UJF, CEA Grenoble, 17 Rue des Martyrs, F-38054 Grenoble, France CEA, INAC/SP2M, Laboratoire SiNaPS, F-38054 Grenoble, France
Bassem Salem
Affiliation:
Laboratoire des Technologies de la Microélectronique (LTM) – UMR 5129 CNRS-UJF, CEA Grenoble, 17 Rue des Martyrs, F-38054 Grenoble, France
Nicolas Pauc
Affiliation:
CEA, INAC/SP2M, Laboratoire SiNaPS, F-38054 Grenoble, France
Pascal Gentile
Affiliation:
CEA, INAC/SP2M, Laboratoire SiNaPS, F-38054 Grenoble, France
Priyanka Periwal
Affiliation:
Laboratoire des Technologies de la Microélectronique (LTM) – UMR 5129 CNRS-UJF, CEA Grenoble, 17 Rue des Martyrs, F-38054 Grenoble, France
Alexis Potié
Affiliation:
Laboratoire des Technologies de la Microélectronique (LTM) – UMR 5129 CNRS-UJF, CEA Grenoble, 17 Rue des Martyrs, F-38054 Grenoble, France
Thierry Baron
Affiliation:
Laboratoire des Technologies de la Microélectronique (LTM) – UMR 5129 CNRS-UJF, CEA Grenoble, 17 Rue des Martyrs, F-38054 Grenoble, France
L. Latu-Romain
Affiliation:
Laboratoire des Technologies de la Microélectronique (LTM) – UMR 5129 CNRS-UJF, CEA Grenoble, 17 Rue des Martyrs, F-38054 Grenoble, France
S. David
Affiliation:
Laboratoire des Technologies de la Microélectronique (LTM) – UMR 5129 CNRS-UJF, CEA Grenoble, 17 Rue des Martyrs, F-38054 Grenoble, France
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Abstract

The authors present the technological routes used to build planar and vertical gate all-around (GAA) field-effect transistors (FETs) using both Si and SiGe nanowires (NWs) and the electrical performances of the as-obtained components. Planar FETs are characterized in back gate configuration and exhibit good behavior such as an ION/IOFF ratio up to 106. Hysteretic behavior and sub-threshold slope values with respect to surface and oxide interface trap densities are discussed. Vertical devices using Si NWs show good characteristics at the state of the art with ION/IOFF ratio close to 106 and sub-threshold slope around 125 mV/decade while vertical SiGe devices also obtained with the same technological processes, present an ION/IOFF ratio from 103 to 104but with poor dynamics which can be explained by the high interface traps density.

Keywords

nanostructureelectrical propertiesdevices
Type
Articles
Information
MRS Online Proceedings Library (OPL) , Volume 1439: Symposium N/AA – Nanowires and Nanotubes-Synthesis, Properties, Devices, and Energy Applications of One-Dimensional Materials , 2012 , pp. 101 - 107
Copyright
Copyright © Materials Research Society 2012

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