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Flip Chip Reliability of GaAs on Si Thinfilm Substrates Using AuSn Solder Bumps

Published online by Cambridge University Press:  01 February 2011

Hermann Oppermann
Affiliation:
Fraunhofer IZM, Gustav-Meyer-Allee 25, D-13355 Berlin, [email protected]; phone: +49 30 46403-163, fax: +49 30 46403-162
Matthias Hutter
Affiliation:
Fraunhofer IZM, Gustav-Meyer-Allee 25, D-13355 Berlin, [email protected]; phone: +49 30 46403-163, fax: +49 30 46403-162
Matthias Klein
Affiliation:
Fraunhofer IZM, Gustav-Meyer-Allee 25, D-13355 Berlin, [email protected]; phone: +49 30 46403-163, fax: +49 30 46403-162
Gunter Engelmann
Affiliation:
Fraunhofer IZM, Gustav-Meyer-Allee 25, D-13355 Berlin, [email protected]; phone: +49 30 46403-163, fax: +49 30 46403-162
Michael Toepper
Affiliation:
Fraunhofer IZM, Gustav-Meyer-Allee 25, D-13355 Berlin, [email protected]; phone: +49 30 46403-163, fax: +49 30 46403-162
Jürgen Wolf
Affiliation:
Fraunhofer IZM, Gustav-Meyer-Allee 25, D-13355 Berlin, [email protected]; phone: +49 30 46403-163, fax: +49 30 46403-162
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Abstract

Au/Sn solder bumps are mainly used for flip chip assembly of compound semiconductors in optoelectronic and RF applications. They allow a fluxless assembly which is required to avoid contamination of optical interfaces and the metallurgy is well suited to the final gold metallization on GaAs or InP. Flip chip assembly experiments were carried out using two layer Au/Sn bumps as plated without prior bump reflow. An RF and reliability test vehicles comprise a GaAs chip which was flip chip soldered on a silicon substrate. Temperature cycling tests with and without underfiller were performed. The different failure modes for underfilled and nonunderfilled samples were discussed and compared. Additional reliability tests were performed with flip chip bonding by gold thermocompression for comparison. The test results and the failure modes are discussed in detail.

Type
Research Article
Copyright
Copyright © Materials Research Society 2005

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