Hostname: page-component-745bb68f8f-cphqk Total loading time: 0 Render date: 2025-01-26T04:41:53.409Z Has data issue: false hasContentIssue false
  • English
  • Français

FE-Modeling and Physical Testing of IGBTs for Press-Packaging

Published online by Cambridge University Press:  10 February 2011

A. Pirondi ,
G. Nicoletito ,
P. Cova ,
M. Pasqualetti ,
M. Portesine ,
P. E. Zani  and
A. Camera
A. Pirondi
Affiliation:
University of Parma, Viale delle Scienze, 43100 Parma – Italy
G. Nicoletito
Affiliation:
University of Parma, Viale delle Scienze, 43100 Parma – Italy
P. Cova
Affiliation:
University of Parma, Viale delle Scienze, 43100 Parma – Italy
M. Pasqualetti
Affiliation:
Ansaldo Trasporti – Semiconductors Unit, Via N. Lorenzi, 8, 16152 Genova – Italy
M. Portesine
Affiliation:
Ansaldo Trasporti – Semiconductors Unit, Via N. Lorenzi, 8, 16152 Genova – Italy
P. E. Zani
Affiliation:
Ansaldo Trasporti – Semiconductors Unit, Via N. Lorenzi, 8, 16152 Genova – Italy
A. Camera
Affiliation:
Ansaldo Trasporti – Semiconductors Unit, Via N. Lorenzi, 8, 16152 Genova – Italy
Get access

Abstract

The reliability of press-packed IGBTs strongly depends on the solutions adopted in terms of heat dissipation and thermo-mechanical stress management so as to guarantee satisfactory electrical and thermal contact conditions throughout the service life. In this paper, two aspects concerning the design process of a single-chip press-pack IGBT are outlined: i) cyclic stresses and strains occurring in the package and in the chip are discussed on the basis of finite element (FE) simulations, ii) a testing rig developed for accelerated testing of single IGBT chips under controlled contact pressure conditions is presented.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 535: Symposium D/I – III-V and IV-IV Materials & Processing Challenges for Highly… , 1998 , 171
Copyright
Copyright © Materials Research Society 1999

Access options

Get access to the full version of this content by using one of the access options below. (Log in options will check for institutional or personal access. Content may require purchase if you do not have access.)

References

1. Darveaux, R., Turlik, I., Hwang, L. T. and Reisman, A., IEEE Trans. Comp. Hybr. Manuf. Technol. 12 (4), 663–672 (1989).Google Scholar
2. Nicoletto, G. et al., in Advances in Electronic Packaging, edited by E., Suhir, M., Shiratori, Lee, Y. C., G., Subbarayan (ASME, New York, 1997), Vol. II, p. 1707.Google Scholar
3. Terzi, M., M. E. thesis, University of Parma, 1997 (in Italian).Google Scholar
4. Kirihata, H., Takahashi, Y., Wakimoto, H., Niino, F., Proc. of JAS Conference, St. Louis, Missouri, USA, Oct. 1998.Google Scholar
5. Barvitius, L., M. E. thesis, University of Parma, 1998 (in Italian).Google Scholar
6. Cova, P., Fantini, F., Microelectronics Reliability 38, 1347 (1998).Google Scholar
7. Pirondi, A. et al., in Power Semiconductor Materials and Devices, edited by Pearton, S. J., Shul, R. J., E., Wolfgang, F., Ren and S., Tenconi (Mater. Res. Soc. Proc. 483, Boston, MA, 1997) p. 39.Google Scholar