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Fabrication of Strain Relaxed Silicon-Germanium-on-Insulator (Si0.35Ge0.65OI) Wafers using Cyclical Thermal Oxidation and Annealing

Published online by Cambridge University Press:  01 February 2011

Grace Huiqi Wang
Affiliation:
[email protected], National University of Singapore, Electrical and Computer Engineering, Silicon Nano Device Lab Engineering drive 3, Singapore, 459441, Singapore
Eng-Huat Toh
Affiliation:
[email protected], National University of Singapore, Singapore, 459441, Singapore
Chih-Hang Tung
Affiliation:
[email protected], Institutue of Microelectronics, Singapaore, 117685, Singapore
Yong-Lim Foo
Affiliation:
[email protected], Institute of Materials Research & Engineering, Singapaore, 117602, Singapore
S. Tripathy
Affiliation:
[email protected], Institute of Materials Research & Engineering, Singapaore, 117602, Singapore
Guo-Qiang Lo
Affiliation:
[email protected], Institutue of Microelectronics, Singapaore, 117685, Singapore
Ganesh Samudra
Affiliation:
[email protected], National University of Singapore, Singapore, 459441, Singapore
Yee-Chia Yeo
Affiliation:
[email protected], National University of Singapore, Singapore, 459441, Singapore
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Abstract

A novel scheme for the fabrication of SiGe-on-insulator (SGOI) substrates comprising a thin and relaxed silicon-germanium (SiGe) layer with high Ge mole fraction is reported.A cyclical thermal oxidation and annealing (CTOA) process is introduced to alleviate issues associated with surface roughening and non-uniformity in Ge content.A systematic study of the stress developed in the SiGe layer as condensation takes place is presented.A clear understanding of the strain evolution enables the SGOI substrate fabrication to be tailored according to the requirements of strain engineering in high mobility MOSFETs.

Type
Research Article
Copyright
Copyright © Materials Research Society 2007

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References

1. Shang, H., Schmidt, H. O., Chan, K. K., Copel, M., Ott, J. A., Kozlowski, P. M., Steen, S. E., Cordes, S. A., Wong, H.-S. P., Jones, E. C. and Haensch, W. E., Technical Dig. International Electron Device Meeting, Dec. 2002, Washington DC, pp. 441444.Google Scholar
2. Wang, H. C.-H, Chen, S.-J., Wang, M.-F., Tsai, P.-Y.; Tsai, C. –W.; Wang, T.-W., Ting, S.M., Hou, T.-H., Lim, P.-S., Lin, H.-J., Jin, Y., Tao, H.-J., Chen, S.-C., Diaz, C.H., Liang, M. –S., Hu, C., Technical Dig. International Electron Device Meeting, Dec. 2002, Washington DC, pp. 161164.Google Scholar
3. Dorner, P., Gust, W., Predel, B., Roll, U., Lodding, A., and Odelius, H., Philos.Mag.A, 49, 557 (1984).Google Scholar
4. Wang, G. H., Toh, E. H., Lim, Y. L., Tung, C.-H., Choy, S.-F., Samudra, G., and Yeo, Y.-C.: Applied. Physics Letters., vol. 89, no.5, pp.31093111, 2006.Google Scholar
5. Mizuno, T., Sugiyama, N., Tezuka, T., Numata, T. and Takagi, S., IEEE Trans. Electron Devices 50, 988 (2003)Google Scholar
6. Tezuka, T., Nakaharai, S., Moriyama, Y., Sujiyama, N. and Takagi, S., Symp. VLSI Tech. Dig. Technical Papers 2004, 7803 (2004).Google Scholar