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Epitaxial and Non-Epitaxial Heterogeneous Integration Technologies at NGST

Published online by Cambridge University Press:  01 February 2011

Augusto Gutierrez-Aitken ,
Patty Chang-Chien ,
Bert Oyama ,
Kelly Tornquist ,
Khanh Thai ,
Dennis Scott ,
Rajinder Sandhu ,
Joe Zhou ,
Peter Nam  and
Wen Phan
Augusto Gutierrez-Aitken
Affiliation:
[email protected], Northrop Grumman Space Technology, Microelectronics, One Space Park, Redondo Beach, CA, 90278, United States
Patty Chang-Chien
Affiliation:
[email protected], Northrop Grumman Space Technology, Redondo Beach, CA, 90278, United States
Bert Oyama
Affiliation:
[email protected], Northrop Grumman Space Technology, Redondo Beach, CA, 90278, United States
Kelly Tornquist
Affiliation:
[email protected], Northrop Grumman Space Technology, Redondo Beach, CA, 90278, United States
Khanh Thai
Affiliation:
[email protected], Northrop Grumman Space Technology, Redondo Beach, CA, 90278, United States
Dennis Scott
Affiliation:
[email protected], Northrop Grumman Space Technology, Redondo Beach, CA, 90278, United States
Rajinder Sandhu
Affiliation:
[email protected], Northrop Grumman Space Technology, Redondo Beach, CA, 90278, United States
Joe Zhou
Affiliation:
[email protected], Northrop Grumman Space Technology, Redondo Beach, CA, 90278, United States
Peter Nam
Affiliation:
[email protected], Northrop Grumman Space Technology, Redondo Beach, CA, 90278, United States
Wen Phan
Affiliation:
[email protected], Northrop Grumman Space Technology, Redondo Beach, CA, 90278, United States
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Abstract

To meet increasingly challenging and complex systems requirements, it is not enough to use one single semiconductor technology but to integrate several high performance technologies in an efficient and cost effective way. Heterogeneous integration (HI) approaches lead to a significant higher design flexibility and performance. In this paper we present some of the HI approaches that are being used and developed at Northrop Grumman Space Technology (NGST) that include selective epitaxial growth, metamorphic growth and wafer level packaging (WLP) technology. More recently we are developing a scaled and selective wafer packaging technique to integrate III-V semiconductors with silicon under the COSMOS DARPA program.

Keywords

devicesIII-Vmicroelectronics
Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 1068: Symposium C – Advances in GaN, GaAs, SiC and Related Alloys on Silicon Substrates , 2008 , 1068-C02-02
Copyright
Copyright © Materials Research Society 2008

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References

REFERENCES

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