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Electrical Properties of Fully Epitaxial PZT/MgO/Si Stacked Structures for Nonvolatile Future Memory Devices

Published online by Cambridge University Press:  10 February 2011

J. Senzaki  and
T. Ueno
J. Senzaki
Affiliation:
Faculty of Technology, Tokyo University of Agriculture and Technology, Koganei, Tokyo 184-8588, Japan, [email protected]
T. Ueno
Affiliation:
Faculty of Technology, Tokyo University of Agriculture and Technology, Koganei, Tokyo 184-8588, Japan
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Abstract

Fully epitaxial Pb (Zr,Ti)O3(PZT)/MgO/Si(001) stacked structures, one of the potential components of ferroelectric-gate FETs, have been fabricated and characterized. According to the structural and electrical characterization of MgO/Si structures, epitaxially grown MgO thin films on the Si substrates showed a small leakage current of ∼ 10−8 A/cm2 at the electric field of 1 MV/cm. In the C-V measurements of the as-grown MgO/Si heteroepitaxial interfaces, injection-type hysteresis was observed because of the crystal defects in the MgO film adjacent to the interface. Using oxygen annealing with a temperature of 400 °C, it showed no hysteresis and a lower interface trap density of the order of 1011 cm−2eV−1 could be achieved with no formation of a low dielectric layer at the MgO/Si interface. These results indicate that the epitaxial MgO thin films are applicable as the gate insulators of FETs. After the PZT film was deposited on the MgO/Si structure, the C-V characteristic of the stacked structure showed a ferroelectric hysteresis curve and the low interface trap density of 5 × 1011 cm−2eV−1 A maximum memory window width of 1.2 V could be obtained in the PZT thin film on the Si substrate with a MgO intermediate layer.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 541: Symposium O – Ferroelectric Thin Films VII , 1998 , 591
Copyright
Copyright © Materials Research Society 1999

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References

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