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The Effects of the LDD process on Short-channel effects in Nanoscale Charge Trapping Devices

Published online by Cambridge University Press:  01 February 2011

Moon Kyung Kim ,
SooDoo Chae ,
Chung Woo Kim ,
Joo Yeon Kim ,
Jo-won Lee  and
Sandip Tiwari
Moon Kyung Kim
Affiliation:
[email protected], Cornell University, Electrical and Computer Engineering, 2250N Triphammer RD L3E, Ithaca, NY, 14850, United States, 607-592-2940
SooDoo Chae
Affiliation:
[email protected], Samsung Electronics Co., Semiconductor Business, Yongin-City, Kyunggi-Do, N/A, Korea, Republic of
Chung Woo Kim
Affiliation:
[email protected], Samsung Electronics Co., Semiconductor Business, Yongin-City, Kyunggi-Do, N/A, Korea, Republic of
Joo Yeon Kim
Affiliation:
[email protected], Ulsan college, School of Electricity & Electronics, Ulsan, 682-715, N/A, Korea, Republic of
Jo-won Lee
Affiliation:
[email protected], Tera-level Nano Devices, Seoul, N/A, Korea, Republic of
Sandip Tiwari
Affiliation:
[email protected], Cornell University, Electrical and Computer Engineering, Ithaca, NY, 14850, United States
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Abstract

In the use of single/few electrons in distributed storage for non-volatile, low power, and fast memories, providing statistical reproducibility at the nanoscale is a key challenge since relative variance has dependence and the devices operate with limited number of storage sites. We have used defects at interfaces of dielectrics to evaluate this reproducibility and the performance of memories. These experiments show that nearly 100 electrons can be stored at 30 nm dimensions, sufficient for reproducibility, and that a minimum of tunneling oxide thickness is required to assure reliable retention characteristics. Different tunneling oxide thicknesses and the effect of LDD process are investigated to draw these conclusions.

Keywords

nanoscalememorydevices
Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 997: Symposium I – Materials and Processes for Nonvolatile Memories II , 2007 , 0997-I03-13
Copyright
Copyright © Materials Research Society 2007

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References

1. Johnson, W., Perlegos, G., Ranganath, T., “A 16Kb electrically erasable nonvolatile memory,” IEEE ISSCC Dig. Tech.Pap.,p.152, 1980 Google Scholar
2. Libsch, F. R. and White, M. H., “Charge Transport and Storage of Low Programming Voltage SONOS Memory Devices,” Solid State Electronics, Vol.33, No.1, p.105–126, 1990.Google Scholar
3. Kim, Moon Kyung, Tiwari, S., “Ultra-short SONOS memories,” IEEE Tran. on nanotechnology, v 3, p. 417–424, 2004.Google Scholar
4. Silva, H., Kim, Moon Kyung, Kumar, A., Avci, U. and Tiwari, S., “Few electron memories: finding the compromise between performance, variability and manufacturability at the NanoScale,” IEDM 2003 Technical Digest p. 271–274, 2003.Google Scholar
5. Stathis, J. H. and DiMaria, D. J., “Reliability Projection for Ultra-Thin Oxide at Low Voltage,” Tech. Dig. of IEDM, p.167–171, 1998.Google Scholar
6. Bu, Jiankang, White, Marvin H., “Design considerations in scaled SONOS nonvolatile memory devices,” Solid-State Electronics, Vol.45, No.1, p.113–120, Jan.2001 Google Scholar