Hostname: page-component-586b7cd67f-rcrh6 Total loading time: 0 Render date: 2024-11-24T17:29:58.105Z Has data issue: false hasContentIssue false

Effect of TaN Stoichiometry on Barrier Oxidation and Defect Density in 32nm Cu/Ultra-Low K Interconnects

Published online by Cambridge University Press:  01 February 2011

Andrew H. Simon
Affiliation:
[email protected], Independent Bulk CMOS and SOI Technology Development Alliance Projects at IBM Microelectronics, Div. Semiconductor Research and Development Center, IBM Microelectronics, Hopewell Junction, New York, United States
Frieder H. Baumann
Affiliation:
[email protected], Independent Bulk CMOS and SOI Technology Development Alliance Projects at IBM Microelectronics, Div. Semiconductor Research and Development Center, IBM Microelectronics, Hopewell Junction, New York, United States
Tibor Bolom
Affiliation:
[email protected], Independent Bulk CMOS and SOI Technology Development Alliance Projects at IBM Microelectronics, Div. Semiconductor Research and Development Center, GLOBALFOUNDRIES Inc, Hopewell Junction, New York, United States
Jong Guk Park
Affiliation:
[email protected], Independent Bulk CMOS and SOI Technology Development Alliance Projects at IBM Microelectronics, Div. Semiconductor Research and Development Center, Samsung Electronics, Hopewell Junction, New York, United States
Craig Child
Affiliation:
[email protected], Independent Bulk CMOS and SOI Technology Development Alliance Projects at IBM Microelectronics, Div. Semiconductor Research and Development Center, GLOBALFOUNDRIES Inc, Hopewell Junction, New York, United States
Ben Kim
Affiliation:
[email protected], Independent Bulk CMOS and SOI Technology Development Alliance Projects at IBM Microelectronics, Div. Semiconductor Research and Development Center, STMicroelectronics, Hopewell Junction, New York, United States
Patrick W. DeHaven
Affiliation:
[email protected], Independent Bulk CMOS and SOI Technology Development Alliance Projects at IBM Microelectronics, Div. Semiconductor Research and Development Center, IBM Microelectronics, Hopewell Junction, New York, United States
Robert E. Davis
Affiliation:
[email protected], Independent Bulk CMOS and SOI Technology Development Alliance Projects at IBM Microelectronics, Div. Semiconductor Research and Development Center, IBM Microelectronics, Hopewell Junction, New York, United States
Oluwafemi O Ogunsola
Affiliation:
[email protected], United States
Matthew S Angyal
Affiliation:
[email protected], Independent Bulk CMOS and SOI Technology Development Alliance Projects at IBM Microelectronics, Div. Semiconductor Research and Development Center, IBM Microelectronics, Hopewell Junction, New York, United States
Get access

Abstract

The scaling of BEOL interconnect technology in ULSI circuitry requires the integration of Cu wiring with ultra-low K (ULK) dielectrics. We present the results of a study of the interaction between different-stoichiometry Ta(N)/Cu barrier processes and porous ULK dielectrics (k=2.4) at 32nm groundrules Auger and diffraction analysis of blanket wafers was used to benchmark two different stoichiometries of TaN barrier deposited using commercially-available ionized PVD sources. Comparison TEM and EDX/EELS images indicates that barrier oxidation is occurring in the low nitrogen-content Ta(N) barrier, which is absent at the higher stoichiometry. These differences are further manifested in defect-density analysis of patterned wafers comparing the two processes. These results illustrate the critical importance the TaN barrier properties play in enabling the integration of Cu/ULK interconnects at 32nm at beyond.

Type
Research Article
Copyright
Copyright © Materials Research Society 2010

Access options

Get access to the full version of this content by using one of the access options below. (Log in options will check for institutional or personal access. Content may require purchase if you do not have access.)

References

1 Edelstein, D. et al. , Tech. Digest, Proc. IEEE Int'l Electron Devices Mtg. 1997, p. 773 Google Scholar
2 Colgan, E.G. Fryer, P.M. U.S. Patent # 5,281,485Google Scholar
3 Edelstein, D. et al. , Proc. IEEE Int'l Interconnect Tech. Conf. 2001, p. 9 Google Scholar
4 Edelstein, D. et al. , Advanced Metallization Conf. 2001, p. 541 Google Scholar
5 Simon, A.H. Uzoh, C.E. U.S. Patent # 5,933,753Google Scholar
6 Simon, A.H. Uzoh, C.E. U.S. Patent # 6,768,203Google Scholar
7 Geffken, R.M. Luce, S.E. U.S. Patent # 5,985,762Google Scholar
8 Alers, G. B. et al. , Proc. IEEE 41st Int'l Reliability Physics Symposium 2003, p. 151 Google Scholar
9 Yang, C.C. et al. , U.S. Patent # 6,784,105Google Scholar
10 Malhotra, S.G. Simon, A.H. U.S. Patent # 6,949,461Google Scholar
11 Yang, C.C. et al. , Proc. IEEE Int'l Interconnect Tech. Conf. 2005, p. 135 Google Scholar
12 Kumar, N. et al. , Advanced Metallization Conf. 2004, p. 247 Google Scholar
13 Thompson, J.H. et al. , European Semicon. Design Production Assembly, v. 23, p. 97 (2001)Google Scholar
14 Simon, A.H. et al. , Proc. of the MRS 2008 Spring Meeting, Symposium N, Pg. 153 Google Scholar