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A Comparison of Spike, Flash, SPER and Laser Annealing for 45nm CMOS

Published online by Cambridge University Press:  01 February 2011

R. Lindsay ,
B. Pawlak ,
J. Kittl ,
K. Henson ,
C. Torregiani ,
S. Giangrandi ,
R. Surdeanu ,
W. Vandervorst ,
A. Mayur  and
J. Ross
...Show all authors
R. Lindsay
Affiliation:
IMEC, Kapeldreef 75, Leuven B3000, Belgium
B. Pawlak
Affiliation:
Philips Research Leuven
J. Kittl
Affiliation:
affiliate researcher at IMEC from Texas Instruments
K. Henson
Affiliation:
IMEC, Kapeldreef 75, Leuven B3000, Belgium
C. Torregiani
Affiliation:
Univ. of Pavia, Pavia, Italy (Masters Stage at Imec)
S. Giangrandi
Affiliation:
Univ. of Pavia, Pavia, Italy (Masters Stage at Imec)
R. Surdeanu
Affiliation:
Philips Research Leuven
W. Vandervorst
Affiliation:
IMEC, Kapeldreef 75, Leuven B3000, Belgium
A. Mayur
Affiliation:
Applied Materials, Santa Clara, CA
J. Ross
Affiliation:
Vortek Industries, Ltd., Vancouver, Canada
S. McCoy
Affiliation:
Vortek Industries, Ltd., Vancouver, Canada
J. Gelpey
Affiliation:
Vortek Industries, Ltd., Vancouver, Canada
K. Elliott
Affiliation:
Vortek Industries, Ltd., Vancouver, Canada
X. Pages
Affiliation:
ASM International n. v, 3723 BC Bilthoven, The Netherlands
A. Satta
Affiliation:
IMEC, Kapeldreef 75, Leuven B3000, Belgium
A. Lauwers
Affiliation:
IMEC, Kapeldreef 75, Leuven B3000, Belgium
P. Stolk
Affiliation:
Philips Research Leuven
K. Maex
Affiliation:
IMEC, Kapeldreef 75, Leuven B3000, Belgium
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Abstract

Due to integration concerns, the use of meta-stable junction formation approaches like laser thermal annealing (LTA), solid phase epitaxial regrowth (SPER), and flash annealing has largely been avoided for the 90nm CMOS node. Instead fast-ramp spike annealing has been optimised along with co-implantation to satisfy the device requirements, often with the help from thin offset spacers. However for the 65nm and 45nm CMOS node it is widely accepted that this conventional approach will not provide the required pMOS junctions, even with changes in the transistor architecture.

In this work, we will compare junction performance and integratablity of fast-ramp spike, flash, SPER and laser annealing down to 45nm CMOS. The junction depth, abruptness and resistance offered by each approach are balanced against device uniformity, deactivation and leakage. Results show that the main contenders for the 45nm CMOS are SPER and flash annealing – but both have to be rigorously optimised for regrowth rates, amorphous positioning and dopant and co-implant profiles. From the two, SPER offers the best junction abruptness (<1nm/dec) with leakage suitable for low power applications, while the flash anneal has the benefit of higher solid solubility (>4E20at/cm3) and less transistor modifications. As expected, Ge and F co-implanted spike annealed junctions do not reach the 45nm node requirements. For full-melt LTA, poly deformation on isolation can be reduced but geometry effects result in unacceptable junction non-uniformity.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 765: Symposium D – CMOS Front-End Materials and Process Technology , 2003 , D7.4
Copyright
Copyright © Materials Research Society 2003

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References

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