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CMP-induced Peeling in Multi-level Ultra Low-k / Cu Interconnects

Published online by Cambridge University Press:  01 February 2011

Patrick Leduc ,
Thierry Farjot ,
Mylène Savoye ,
Anne-Cécile Demas ,
Sylvain Maitrejean  and
Gerard Passemard
Patrick Leduc
Affiliation:
[email protected], CEA-LETI, Nanotec department, 17, avenue des Martyrs, Grenoble, N/A, F-38054, France, 33 4 38 78 24 07, 33 4 38 78 30 34
Thierry Farjot
Affiliation:
[email protected], CEA-LETI, 17 avenue des Martyrs, Grenoble, N/A, F-38054, France
Mylène Savoye
Affiliation:
[email protected], CEA-LETI, 17 avenue des Martyrs, Grenoble, N/A, F-38054, France
Anne-Cécile Demas
Affiliation:
[email protected], CEA-LETI, 17 avenue des Martyrs, Grenoble, N/A, F-38054, France
Sylvain Maitrejean
Affiliation:
[email protected], CEA-LETI, 17 avenue des Martyrs, Grenoble, N/A, F-38054, France
Gerard Passemard
Affiliation:
[email protected], STMicroelectronics, 850 rue Jean Monnet, Crolles, N/A, F38926, France
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Abstract

This work shows that the addition of dielectric levels in interconnect stacks increases significantly the CMP-induced peeling. The fracture energies, measured by 4-point bending technique, are less sensitive to the level number increase, even if they are slightly degraded. This leads to the conclusion that delamination during polishing depends highly on the stack elastic properties and there is no simple correlation between stack adhesion and peeling during CMP. In this work, mechanical damages generated during CMP in the dielectric stack before peeling were also investigated. It was shown that, if no peeling appears, CMP have no effect on stack reliability. This indicates that negligible “fatigue” effect takes place during CMP.

Keywords

CMPelastic propertiesfracture
Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 914: Symposium F – Materials, Technology and Reliability of Low-k Dielectrics and Copper Interconnects , 2006 , 0914-F12-07
Copyright
Copyright © Materials Research Society 2006

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