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CMP Revisited for the MEMS/Foundry Era

Published online by Cambridge University Press:  01 February 2011

Lawrence Camilletti  and
Jazz Semiconductor
Lawrence Camilletti
Affiliation:
Newport Beach, CA
Jazz Semiconductor
Affiliation:
Newport Beach, CA
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Abstract

Business/foundry driven requirements have necessitated the creation of modified ILD CMP processes for terminal metal-die planarization for BiCMOS SOC/MEMS applications. Therefore, despite much CMP process evolution, this paper ‘steps-back’ to test CMP assumptions first introduced within ILD process norms on these new applications at 10X typical process topographies. Evaluation of planarization targets, density effects, oxide budgets, as well as associated integration, throughput and metrology considerations within this expanded regime are discussed. ANOVA on inter- and intra-die (WIWNU and WIDNU) variation are used to quantify results throughout the work.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 767: Symposium F – Chemical-Mechanical Planarization , 2003 , F5.7
Copyright
Copyright © Materials Research Society 2003

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References

1. Stine, B., Boning, D. et al. , “The Physical and Electrical Effects of Metal-fill Patterning Practices for Oxide CMP Processes”, IEEE Transactions on Electron Devices, vol. 45 (no. 3); pp. 665–79, 1998.Google Scholar
2. Camilletti, L., “Implementation of CMP-based Design Rules and Patterning Practices”, 1995 IEEE/SEMI Advanced Semiconductor Manufacturing Conference, pp.2–4.Google Scholar