Hostname: page-component-cd9895bd7-mkpzs Total loading time: 0 Render date: 2024-12-24T18:37:53.414Z Has data issue: false hasContentIssue false
  • English
  • Français

Backside Copper Contamination Issues in CMOS Process Integration – A Case Study

Published online by Cambridge University Press:  17 March 2011

K. Prasad ,
K.C. Tee ,
L. Chan  and
A. K. See
K. Prasad
Affiliation:
School of Electrical & Electronic Engineering Nanyang Technological University Nanyang Avenue, Singapore 639798
K.C. Tee
Affiliation:
School of Electrical & Electronic Engineering Nanyang Technological University Nanyang Avenue, Singapore 639798
L. Chan
Affiliation:
R&D Department Chartered Semiconductor Manufacturing Limited 60 Woodlands Industrial Park Street II, Singapore 738406
A. K. See
Affiliation:
R&D Department Chartered Semiconductor Manufacturing Limited 60 Woodlands Industrial Park Street II, Singapore 738406
Get access

Abstract

NMOS and PMOS transistors of various (W/L) ratios, down to 0.24µm channel length, have been used to investigate the effects of copper diffusion (from the backside) on their electrical parameters. A thin layer of copper film was deposited on the back surface of the wafer. Over 10 hours of annealing at 4000C was carried out. Electrical parameters such as the threshold voltage (VT0), the drain saturation current (IDsat) and the off-current (Ioff), for transistors, and the leakage current for large diodes were measured. Secondary Ion Mass Spectroscopy (SIMS) was used to monitor the copper diffusion. Even after 10 hours of annealing at 400°C, electrical parameters of both NMOS and PMOS devices and leakage currents of diodes showed no significant degradation.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 612: Symposium D – Materials, Technology & Reliability for Advanced Interconnects.. , 2000 , D8.4.1
Copyright
Copyright © Materials Research Society 2000

Access options

Get access to the full version of this content by using one of the access options below. (Log in options will check for institutional or personal access. Content may require purchase if you do not have access.)

References

1. Wang, Shi-Qing, MRS bulletin, 30, (1994).Google Scholar
2. Istratov, A. A., Flink, C., Hieslmair, H., Heiser, T., and Weber, E. R., Appl. Phys. Lett. 71, 2121, (1997).10.1063/1.119355Google Scholar
3. Istratov, A. A., Hieslmair, H., Flink, C., Heiser, T., and Weber, E. R., Appl. Phys. Lett. 71, 2349, (1997).10.1063/1.120026Google Scholar
4. Ho, C.S., Pey, K.L., Wong, H., Lee, K.H., Karunasiri, R.P.G., Chua, S.J., Tang, Y., Wong, S.M., Chan, L.H., Proc. 14th International VLSI Multilevel Interconnection Conference, Santa Clara, USA, 396, (1997).Google Scholar
5. Thompson, R.D., and Tu, K.N., Appl. Phys. Lett, 41, 440, (1982).10.1063/1.93565Google Scholar
6. Stolt, L., Dheurie, F.M. and Harper, J.M.E., Thin Solid Films, 200, 147 (1991).10.1016/0040-6090(91)90037-XGoogle Scholar
7. Rotondaro, A.L.P., Vandamme, E., Vanhellemont, J., Simoen, E., Heyns, M.M. and Claeys, C., Solid State Phenomena, 47–48, 397, (1996).Google Scholar
8. Hozawa, K., Itogo, T., Isomae, S., and Ohkura, M., 1999 Symposium on VLSI Technology, Tokyo, (1999).Google Scholar
9. Sze, S.M., “VLSI Technology”, 2nd Edition, McGraw-Hill (USA), (1988).Google Scholar
10. Harsanyi, G., IEEE Electron Device Lett., 20, 5, (1999)10.1109/55.737556Google Scholar
11. Vermiere, B., Lee, L., and Parks, H.G., IEEE Trans. Semicond. Manufacuturing, 11, 232, (1998).10.1109/66.670169Google Scholar