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Application of Analogue Amorphous Silicon Memory Devices to Resistive Synapses for Neural Networks

Published online by Cambridge University Press:  21 February 2011

A A Reeder
Affiliation:
British Telecom Laboratories, Martlesham Heath, Suffolk, England
I P Thomas
Affiliation:
British Telecom Laboratories, Martlesham Heath, Suffolk, England
C Smith
Affiliation:
British Telecom Laboratories, Martlesham Heath, Suffolk, England
J Wittgreffe
Affiliation:
British Telecom Laboratories, Martlesham Heath, Suffolk, England
D J Godfrey
Affiliation:
British Telecom Laboratories, Martlesham Heath, Suffolk, England
J Hajto
Affiliation:
Department of Electrical Engineering, University of Edinburgh, Edinburgh, Scotland
A E Owen
Affiliation:
British Telecom Laboratories, Martlesham Heath, Suffolk, England
A J Snell
Affiliation:
British Telecom Laboratories, Martlesham Heath, Suffolk, England
A F Murray
Affiliation:
Department of Electrical Engineering, University of Edinburgh, Edinburgh, Scotland
M J Rose
Affiliation:
Department of Applied Physics, University of Dundee, Dundee, Scotland.
I S Osborne
Affiliation:
Department of Applied Physics, University of Dundee, Dundee, Scotland.
P G LeComber
Affiliation:
Department of Applied Physics, University of Dundee, Dundee, Scotland.
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Abstract

The amorphous silicon memory device shows promise as an analogue weight element in neural networks. The device resistance can be programmed to within 5% of any specific value between lkΩ and lMΩ using 10ns to 1μ voltage pulses in the range 1–5V. In this paper we describe the physical structure of the element and its electrical characteristics. Finally, a simple example is discussed of a small neural network implementing the EXOR function using amorphous silicon memory elements as a resistive array of weights and external op-amps as the current summing nodes.

Type
Research Article
Copyright
Copyright © Materials Research Society 1992

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References

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