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Aligned Low Temperature Wafer Bonding for MEMS Manufacturing: Challenges and Promises

Published online by Cambridge University Press:  01 February 2011

Viorel Dragoi
Affiliation:
[email protected], EV Group, Technology, DI Erich Thallner Str. 1, St. Florian am Inn, N/A, Austria, +43771253110
Thorsten Matthias
Affiliation:
[email protected], EV Group Inc., Technology, 7700 South River Parkway, Tempe, AZ, 85284, United States
Gerald Mittendorfer
Affiliation:
[email protected], EV Group, Technology, DI Erich Thallner Str. 1, St. Florian am Inn, Austria
Paul Lindner
Affiliation:
[email protected], EV Group, Technology, DI Erich Thallner Str. 1, St. Florian am Inn, Austria
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Abstract

The increased complexity of current generations of MEMS devices imposes new requirements for wafer bonding. Among these can be mentioned low process temperature (<400°C), precise optical alignment of substrates, ability to bond a large variety of substrates and the possibility to bond with defined intermediate layers. An important aspect in aligned wafer bonding is that alignment accuracy needs to be correlated to the type of bond process. Especially in case of processes using bonding layers the post-bond alignment accuracy will be given by the behavior of the bonding layers. This paper aims to review the main criteria to be considered in defining aligned wafer bonding processes. Particularly bonding of substrates containing electronics (e.g. CMOS wafers) is currently of high technological interest.

Type
Research Article
Copyright
Copyright © Materials Research Society 2008

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