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Advanced Al Damascene Process for Fine Trench Under 70nm Design Rule

Published online by Cambridge University Press:  01 February 2011

Sung Ho Han ,
Kyung-In Choi ,
Sera Yun ,
Jeong Heon Park ,
Won Sok Lee ,
Sang Woo Lee ,
Gil Heyun Choi ,
Change Kee Hong ,
Sung Tae Kim  and
Uin Chung
...Show all authors
Sung Ho Han
Affiliation:
Process Development Team, Semiconductor R&D Center, Samsung Electronics Co. Ltd., San#24 Nongseo-Ri, Kiheung-Eup, Yongin-City, Kyungki-Do 449-711, Korea Phone: 82-31-209-3663, Fax: 82-31-209-6299, E-mail: [email protected]
Kyung-In Choi
Affiliation:
Process Development Team, Semiconductor R&D Center, Samsung Electronics Co. Ltd., San#24 Nongseo-Ri, Kiheung-Eup, Yongin-City, Kyungki-Do 449-711, Korea Phone: 82-31-209-3663, Fax: 82-31-209-6299, E-mail: [email protected]
Sera Yun
Affiliation:
Process Development Team, Semiconductor R&D Center, Samsung Electronics Co. Ltd., San#24 Nongseo-Ri, Kiheung-Eup, Yongin-City, Kyungki-Do 449-711, Korea Phone: 82-31-209-3663, Fax: 82-31-209-6299, E-mail: [email protected]
Jeong Heon Park
Affiliation:
Process Development Team, Semiconductor R&D Center, Samsung Electronics Co. Ltd., San#24 Nongseo-Ri, Kiheung-Eup, Yongin-City, Kyungki-Do 449-711, Korea Phone: 82-31-209-3663, Fax: 82-31-209-6299, E-mail: [email protected]
Won Sok Lee
Affiliation:
Process Development Team, Semiconductor R&D Center, Samsung Electronics Co. Ltd., San#24 Nongseo-Ri, Kiheung-Eup, Yongin-City, Kyungki-Do 449-711, Korea Phone: 82-31-209-3663, Fax: 82-31-209-6299, E-mail: [email protected]
Sang Woo Lee
Affiliation:
Process Development Team, Semiconductor R&D Center, Samsung Electronics Co. Ltd., San#24 Nongseo-Ri, Kiheung-Eup, Yongin-City, Kyungki-Do 449-711, Korea Phone: 82-31-209-3663, Fax: 82-31-209-6299, E-mail: [email protected]
Gil Heyun Choi
Affiliation:
Process Development Team, Semiconductor R&D Center, Samsung Electronics Co. Ltd., San#24 Nongseo-Ri, Kiheung-Eup, Yongin-City, Kyungki-Do 449-711, Korea Phone: 82-31-209-3663, Fax: 82-31-209-6299, E-mail: [email protected]
Change Kee Hong
Affiliation:
Process Development Team, Semiconductor R&D Center, Samsung Electronics Co. Ltd., San#24 Nongseo-Ri, Kiheung-Eup, Yongin-City, Kyungki-Do 449-711, Korea Phone: 82-31-209-3663, Fax: 82-31-209-6299, E-mail: [email protected]
Sung Tae Kim
Affiliation:
Process Development Team, Semiconductor R&D Center, Samsung Electronics Co. Ltd., San#24 Nongseo-Ri, Kiheung-Eup, Yongin-City, Kyungki-Do 449-711, Korea Phone: 82-31-209-3663, Fax: 82-31-209-6299, E-mail: [email protected]
Uin Chung
Affiliation:
Process Development Team, Semiconductor R&D Center, Samsung Electronics Co. Ltd., San#24 Nongseo-Ri, Kiheung-Eup, Yongin-City, Kyungki-Do 449-711, Korea Phone: 82-31-209-3663, Fax: 82-31-209-6299, E-mail: [email protected]
Joo Tae Moon
Affiliation:
Process Development Team, Semiconductor R&D Center, Samsung Electronics Co. Ltd., San#24 Nongseo-Ri, Kiheung-Eup, Yongin-City, Kyungki-Do 449-711, Korea Phone: 82-31-209-3663, Fax: 82-31-209-6299, E-mail: [email protected]
Byung-Il Ryu
Affiliation:
Process Development Team, Semiconductor R&D Center, Samsung Electronics Co. Ltd., San#24 Nongseo-Ri, Kiheung-Eup, Yongin-City, Kyungki-Do 449-711, Korea Phone: 82-31-209-3663, Fax: 82-31-209-6299, E-mail: [email protected]
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Abstract

Due to a rapid shrinkage in memory devices, backned of the line process experiences great difficulties, especially Al metallization. Furthermore, there is a continuous demands in low line resistance in order to promote device performances. In this article, Al damascene process is proposed as compared to Al patterning process, which suffers from inherent pattering issue at a fine pitch under 70nm. The most difficulties in the development of Al damascene process were to form a stable and void free Al in fine trench and to obtain scratch and corrosions free Al surface. In this study, 50nm beyond fill was successfully achieved by “bottom up growth” of CVD Al. For the process, CVD Al by using Methylpyrroridine Alane (MPA) precursor was deposited on a stacked film of CVD TiN and PVD TiN as a wetting layer, which was followed by PVD Al and reflow, then the Al surface was polished with colloidal silica based slurry.

In addition, electrical property of Al scheme and W scheme was compared with damascene pattern, along with which we demonstrated that around 36% decrease in parasitic capacitance is achievable by decrease of metal line height from 3500A to 1000A on simulation test implying that device performance could be enhanced.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 863: Symposium B – Materials, Technology and Reliability of Advanced Interconnects , 2005 , B8.23
Copyright
Copyright © Materials Research Society 2005

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References

1. Lee, J.M.et al., Proc. of the International Interconnect Technology Conference, 72 (2001)Google Scholar
2. Seo, Jung Hunet al., IITC2003Google Scholar