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The Use of SiGe Barriers During the Formation of p+ Shallow Junctions by Ion Implantation

Published online by Cambridge University Press:  17 March 2011

Phillip E. Thompson ,
Joe Bennett  and
Susan Felch
Phillip E. Thompson
Affiliation:
Code 6812, Naval Research Laboratory, Washington, DC 20375, USA
Joe Bennett
Affiliation:
International SEMATECH, Austin TX 78741, USA
Susan Felch
Affiliation:
Applied Materials, Sunnyvale, CA 94086, USA
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Abstract

Ultra-shallow p+ junctions are required for next generation electronics. We present a technique for the formation of ultra-shallow p+ junctions that increases the thermal stability of the junctions formed by ion implantation. By using a 10 nm Si1−xGex barrier layer, the diffusion of B is inhibited during high temperature processes. Alloys having a composition from x = 0 to 0.4 were investigated and it is shown that the most effective barrier had the maximum Ge fraction. The junction depth decreased to 36.7 nm for a 5×1015/cm2 1kV BF3 plasma implant spike annealed at 1050°C, compared to a junction depth of 48 nm for a Si control sample having the identical implant and anneal. It is hypothesized that the inhibition of B diffusion in the alloy layer is caused by a reduction of the Si self-interstitials in the alloy.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 810: Symposium C – Silicon Front-End Junction Formation-Physics and Technology , 2004 , C4.11
Copyright
Copyright © Materials Research Society 2004

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