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•• Recent Progress in Ferroelectic-gate FETs

Published online by Cambridge University Press:  11 February 2011

Hiroshi Ishiwara  and
Byung-Eun Park
Hiroshi Ishiwara
Affiliation:
Frontier Collaborative Research Center andTokyo Institute of Technology, 4259 Nagatsuda, Midoriku, Yokohama 226–8503 Japan
Byung-Eun Park
Affiliation:
Precision and Intelligence Laboratory, Tokyo Institute of Technology, 4259 Nagatsuda, Midoriku, Yokohama 226–8503 Japan
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Abstract

Recent progress in the research of ferroelectric-gate FETs is reviewed mainly from a view-point of the data retention characteristics. First, importance of insulator-inserted gate structures such as an MFIS (M; metal, F; ferroelectric, I; insulator, S; semiconductor) or MFMIS structure is described and the necessary conditions for the insulating buffer layer and the ferroelectric film are discussed. Then, experimental results for the SiO2 and high-k dielectric buffer layers combined with such ferroelectric films as SBT (SrBi2Ta2O9) and BLT ((Bi,La)4Ti3O12) are presented, in which particular attention is paid to the discussion on the induced charge matching between the buffer layer and the ferroelectric film. As an example, it is shown in a Pt/BLT/LaAlO3/Si diode that the high and low capacitance values written by positive and negative pulses can be retained at least for 3 days. Finally, recent experimental results on the data retention characteristics of the ferroelectric-gate FETs are presented.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 748: Symposium U – Ferroelectric Thin Films XI , 2002 , U9.5/T4.5
Copyright
Copyright © Materials Research Society 2003

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References

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