Hostname: page-component-78c5997874-mlc7c Total loading time: 0 Render date: 2024-11-07T23:05:05.023Z Has data issue: false hasContentIssue false
  • English
  • Français

Pseudo-MOS Operation of Ultra-Narrow Polycrystalline Silicon Wires: Electrical Characterization and Memory Effects

Published online by Cambridge University Press:  17 March 2011

C. Anghel ,
N. Hefyene ,
A.M. Ionescu ,
M. Declercq ,
J.W. Tringe  and
J.D. Plummer
C. Anghel
Affiliation:
Swiss Federal Institute of Technology Lausanne, Electronics Laboratory, ELB Ecublens, CH-1015, Lausanne, Switzerland
N. Hefyene
Affiliation:
Swiss Federal Institute of Technology Lausanne, Electronics Laboratory, ELB Ecublens, CH-1015, Lausanne, Switzerland
A.M. Ionescu
Affiliation:
Swiss Federal Institute of Technology Lausanne, Electronics Laboratory, ELB Ecublens, CH-1015, Lausanne, Switzerland
M. Declercq
Affiliation:
Swiss Federal Institute of Technology Lausanne, Electronics Laboratory, ELB Ecublens, CH-1015, Lausanne, Switzerland
J.W. Tringe
Affiliation:
Center for Integrated Systems, Stanford University, Stanford, CA 94305-4070, U.S.A
J.D. Plummer
Affiliation:
Center for Integrated Systems, Stanford University, Stanford, CA 94305-4070, U.S.A
Get access

Abstract

This paper presents a new method for the electrical characterization of polycrystalline silicon wires based on the pseudo-MOS effect. The investigated devices are ultra-narrow (0.1- 0.2μm), four-contact polycrystalline silicon wires composed of several individual grains in series. The pseudo-MOS static operation allow the examination of interface and bulk characteristics via MOSFET modeling in terms of electrical parameters (carrier mobility, flat band and threshold voltages, mobility reduction coefficient). Additionally, the measurement of 1/f noise is shown to be a useful complementary characterization tool for material investigation. Particular attention is paid to the exploration of transient phenomena in the dynamic pseudo-MOS operation. A significant I-V hysteresis is experimentally revealed when high voltages are applied on the substrate acting as a gate. Long current relaxation (>100s) in accumulation and depletion, in darkness and under illumination, demonstrate the dominance of carrier trapping at grain boundaries over oxide charging and/or SRH generation-recombination intra-grain phenomena. The dynamic regime analysis shows remarkable data retention duration and suggest further investigations of polycrystalline silicon wires for memory applications may be useful.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 638: Symposium F – Microcrystaline & Nanocrystalline Semiconductors-2000 , 2000 , F12.4.1
Copyright
Copyright © Materials Research Society 2001

Access options

Get access to the full version of this content by using one of the access options below. (Log in options will check for institutional or personal access. Content may require purchase if you do not have access.)

References

1. Yano, K., Ishii, T., Sano, T., Mine, T., Murai, F., Hashimoto, T., Kobayashi, T., Kure, T., Seki, K., Single-Electron Memory for Giga-to-Tera bit Storage, Proc. IEEE, 87, 633 (1999).Google Scholar
2. Kim, K., Hwang, C.G., Lee, J.G., DRAM Technology Perspective for Gigabit Era, IEEE Trans. Electron Dev., 45, 598 (1998).Google Scholar
3. Ionescu, A.M., Tringe, J.W., Chovet, A. and Plummer, J.D., On a Novel Technique for the Electrical Characterization of Polycrystalline Silicon, Proc ESSDERC 2000, ed. Lane, W.A., Crean, G.M., McCabe, F.A., Grunbacher, H. (Frontier Group, 2000), pp. 420–423.Google Scholar
4. Tringe, J.W. and Plummer, J.D., Electrical and structural properties of polycrystalline silicon, Journal of Applied Physics, 8, 7913 (2000).Google Scholar
5. Yano, K., Ishii, T., Hashimoto, T., Kobayashi, T., Murai, F., Seki, K., Room-Temperature Single-Electron Memory, IEEE Trans. Electron Dev., 41, 1628 (1994).Google Scholar