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The Positive Gate Bias Annealing Method for the Suppression of a Leakage Current in the SPC-Si TFT on a Glass Substrate

Published online by Cambridge University Press:  01 February 2011

Sang-Geun Park ,
Joong-Hyun Park ,
Seung-Hee Kuk ,
Dong-Won Kang  and
Min-Koo Han
Sang-Geun Park
Affiliation:
[email protected], Seoul National University, School of electrical engineering science, 130Dong-305Ho San 56-1 Shilim 9 Dong Gwanak-Gu, Seoul, 151-742, Korea, Republic of
Joong-Hyun Park
Affiliation:
[email protected], Seoul National University, School of electrical engineering science, 130Dong-305Ho San 56-1 Shilim 9 Dong Gwanak-Gu, Seoul, 151-742, Korea, Republic of
Seung-Hee Kuk
Affiliation:
[email protected], Seoul National University, School of electrical engineering science, 130Dong-305Ho San 56-1 Shilim 9 Dong Gwanak-Gu, Seoul, 151-742, Korea, Republic of
Dong-Won Kang
Affiliation:
[email protected], Seoul National University, School of electrical engineering science, 130Dong-305Ho San 56-1 Shilim 9 Dong Gwanak-Gu, Seoul, 151-742, Korea, Republic of
Min-Koo Han
Affiliation:
[email protected], Seoul National University, School of electrical engineering science, 130Dong-305Ho San 56-1 Shilim 9 Dong Gwanak-Gu, Seoul, 151-742, Korea, Republic of
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Abstract

We fabricated PMOS SPC-Si TFTs which show better current uniformity than ELA poly-Si TFTs and superior stability compare to a-Si:H TFT on a glass substrate employing alternating magnetic field crystallization. However the leakage current of SPC-Si TFT was rather high for circuit element of AMOLED display due to many grain boundaries which could be electron hole generation centers. We applied off-state bias annealing of VGS=5V, VDS=−20V in order to suppress the leakage current of SPC-Si TFT. When the off-state bias annealing was applied on the SPC-Si TFT, the electron carriers were trapped in the gate insulator by high gate-drain voltage (25V). The trapped electron carriers could reduce the gate-drain field, so that the leakage current of SPC-Si TFT was reduced after off-state bias annealing. We applied AC-bias stress on the gate node of SPC-Si TFT for 20,000 seconds in order to verify that the leakage current of SPC-Si TFT could be remained low at actual AMOLED display circuit after off-state bias annealing. The suppressed leakage current was not altered after AC-bias stress. The off-state bias annealed SPC-Si TFT could be used as pixel element of high quality AMOLED display.

Keywords

displaySithin film
Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 1066: Symposium A – Amorphous and Polycrystalline Thin-Film Silicon Science and Technology—2008 , 2008 , 1066-A13-03
Copyright
Copyright © Materials Research Society 2008

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References

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