Optimization of Poly-silicon Process for 3C-SiC Based MOS Devices

Abstract

Cubic 3C-SiC is regarded as a perfect material for medium power MOSFETs with blocking voltages of around 1500V and current handling of 100A and more. One of the main issues to realize such power MOSFETs is the improvement of the MOS gate to ensure low on-state resistance operation.

The benefits of the implementation of an advanced oxidation process combining PECVD SiO₂ deposition and short post-oxidation steps in wet oxygen has been previously demonstrated [1]. The concentrations of fixed and mobile charges in the oxide and at the SiO₂/SiC interface were significantly reduced. But the optimization of the gate material is still an issue.

The experiences from silicon technology point in the direction of using a poly-Si gate for MOS controlled devices. Significant improvements in terms of gate oxide reliability could be achieved by applying a poly-Si gate. But the usage of hydrogen for passivation of defects in oxides grown on 3C-SiC gives restrictions to the poly-Si deposition and activation process conditions. A reduced thermal budget is required to preserve the high electrical properties of the oxide.

We investigated the electrical properties of MOS structures prepared with poly-Si gates. The poly-Si layer was deposited by the LPCVD technique mixing Si₂H₆ and PH₃ at 380°C. The poly-Si activation has been carried out with five different methods. The influence of the following two main parameters has been considered: the process duration (thermal annealing or rapid thermal annealing) and the gas atmosphere (argon, dry or wet oxygen).

MOS capacitors were fabricated on the oxidized free-standing n-type 3C-SiC (001) wafers with 5μm low nitrogen doped (5×10¹⁵ cm^-3) epitaxial layers. The MOS capacitors were characterized on the wafer level (about 200 MOS structures per wafer) by capacitance-conductance-voltage (C-G-V) measurements using a HP4284A LCR meter in the frequency range of 100 Hz to 1 MHz. The measurements were performed at room temperature in a light-tight and electrically shielded environment. The interface trap densities Dit were extracted by the conductance method. To assess the oxide reliability, time-zero dielectric breakdown (TZDB) measurements were conducted on the fabricated MOS structures.

The optimized poly-Si activation process based on RTA in argon has minimal thermal budget and preserves the oxide and interface quality. The fabricated MOS structures demonstrate high electrical properties and reliability of the oxide: A small negative flat band voltage shift of -1V and an interface state density Dit of 7.4×10¹⁰ eV^-1cm^-2 at 0.63 eV below the conduction band. The TZDB measurements revealed an average breakdown electric field of 9.4 MV/cm.