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A Novel CMP Process on Fixed Abrasive Pads for the Manufacturing of Highly Planar Thick Film SOI Substrates

Published online by Cambridge University Press:  01 February 2011

Martin Kulawski
Affiliation:
VTT Microelectronics, Tietotie 3, P.O. Box 1208, FIN-02044 VTT; Espoo; Finland
Kimmo Henttinen
Affiliation:
VTT Microelectronics, Tietotie 3, P.O. Box 1208, FIN-02044 VTT; Espoo; Finland
Ilkka Suni
Affiliation:
VTT Microelectronics, Tietotie 3, P.O. Box 1208, FIN-02044 VTT; Espoo; Finland
Frauke Weimar
Affiliation:
M Laboratories (Europe); Carl-Schurz-Str.1; D-41453 Neuss; Germany
Jari Mäkinen
Affiliation:
Okmetic Oy; Sinimäentie 12; P.O. Box 44; FIN-01301 Vantaa; Finland Contact: [email protected]
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Abstract

A new approach using Fixed Abrasive (FA) pads has been undertaken to overcome the problem of non-uniform thick film Silicon-on-Insulator (SOI) wafers after CMP polishing. The theoretical models indicating the advantages of the 2-body system of the fixed abrasive configuration vs. the conventional 3-body system of slurry based polishing have been convincingly demonstrated in practise upon experiments in a wide range of parameters. As a result it is possible to maintain or improve the flatness of wafers after back grinding, while simultaneously removing the sub-surface damage. A surface quality of prime wafers can be reached on the device layer. Capacitive thickness measurement scans and atomic force microscopy (AFM) monitoring confirm the results. A detailed comparison with conventional processing has been carried out to clarify the advantages on bulk silicon wafers. Decoration etching is used to analyse the wafer surface quality in terms of oxide induced stacking faults (OISF). As a result an alternative processing method is proposed for manufacturing thick film SOI substrates with improved uniformity.

Type
Research Article
Copyright
Copyright © Materials Research Society 2003

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References

[1]: Henley, Francois J. & Current, Michael I., Semiconductor Fabtech, 12th Edition, PP.204 Google Scholar