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Modeling and Fabrication of Cladded Ge Quantum Dot Gate Silicon MOSFETs Exhibiting 3-State Behavior

Published online by Cambridge University Press:  01 February 2011

Faquir C. Jain ,
Mukesh Gogna ,
Fuad Alamoody ,
Supriya Karmakar ,
Ernesto Suarez ,
John Chandy  and
Evan Heller
Faquir C. Jain
Affiliation:
[email protected], University of Connecticut, ECE, Storrs, Connecticut, United States
Mukesh Gogna
Affiliation:
[email protected], University of Connecticut, Storrs, United States
Fuad Alamoody
Affiliation:
[email protected], University of Connecticut, Storrs, United States
Supriya Karmakar
Affiliation:
[email protected], University of Connecticut, Storrs, United States
Ernesto Suarez
Affiliation:
[email protected], University of Connecticut, Storrs, United States
John Chandy
Affiliation:
[email protected], University of Connecticut, Storrs, United States
Evan Heller
Affiliation:
[email protected], RSoft Design Group, Ossinings, New York, United States
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Abstract

This paper presents electrical transfer (Id-Vg) and output (Id-Vds) characteristics of a GeOx-cladded-Ge quantum dot (QD) gate Si MOSFET devices. In QD gate FETs, the manifestation of an intermediate state ‘i” makes it a 3-state device. The intermediate state originates due to compensation of increment in the gate voltage by a similar increase in the threshold voltage, which occurs via charge neutralization in the QD gate due to transfer of charge from the inversion layer to either first or second of the two QD layers.

Keywords

self-assemblynanostructuremicroelectronics
Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 1108: Symposium A – Performance and Reliability of Semiconductor Devices , 2008 , 1108-A05-04
Copyright
Copyright © Materials Research Society 2009

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References

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