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Interfacial Layer Growth Condition Dependent Electrical Conduction in HfO2/SiO2 Heterostructured thin films

Published online by Cambridge University Press:  19 March 2012

Santosh K. Sahoo
Affiliation:
National Renewable Energy Laboratory, 1617 Cole Blvd., Golden, Colorado 80401, USA New Jersey Institute of Technology, Newark, New Jersey 07102, USA
D. Misra
Affiliation:
New Jersey Institute of Technology, Newark, New Jersey 07102, USA
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Abstract

The electrical conduction mechanism contributing to the leakage current at different field regions has been studied in this work. The current-voltage (I-V) measurement of TiN/HfO2/SiO2/P-Si nMOS capacitor has been taken for two different interfacial layer (SiO2) growth conditions such as in situ steam grown (ISSG) and chemical processes. It is observed that Poole-Frenkel mechanism is the dominant conduction mechanism in high field region whereas Ohmic conduction is dominant in the low field region. Also it is seen that the gate leakage current is reduced for the devices having chemically grown interfacial layer compared to that of ISSG devices. Both trap energy level (ϕt) and activation energy (Ea) increase in the chemically grown interfacial layer devices for the Poole-Frenkel and Ohmic conduction mechanisms respectively in comparison to ISSG devices. Trap energy level (ϕt) of ~ 0.2 eV, obtained from Poole-Frenkel mechanism indicates that the doubly ionized oxygen vacancies (V2-) are the active defects and are contributing to the leakage current in these devices.

Type
Research Article
Copyright
Copyright © Materials Research Society 2012

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References

REFERENCES

1. Chaudhuri, A. R. and Krupanidhi, S. B., J. Appl. Phys. 98, 094112 (2005).Google Scholar
2. Weste, N. H. E and Harris, D., CMOS VLSI Design: A circuit and system perspective, 3 rd ed. (Addison-Wesley, Boston, 2005).Google Scholar
3. Kim, Hyoungsub, Marshall, Ann, Mclntyre, Paul C., and Saraswat, Krishna C., Appl. Phys. Lett. 84, 2064 (2004).Google Scholar
4. Campera, A., Iannaccone, G., Crupi, F., IEEE Trans. Electron Devices 54, 83 (2007).Google Scholar
5. Chiu, F.-C., J. Appl. Phys. 100, 114102 (2006).Google Scholar
6. Mitrovic, I.Z., Lu, Y., Buiu, O., Hall, S., Microelectronics Engg. 84, 2306 (2007).Google Scholar
7. Chowdhury, N.A., Wang, X., Bersuker, G., Young, C., Rahim, N. and Misra, D., Microelectronics Reliab. 49, 495 (2009).Google Scholar
8. Sze, S.M., Physics of Semiconductor Devices, 2 nd ed., Wiley-Interscience,(1981).Google Scholar
9. Xu, Z., Houssa, M., De Gendt, S., and Heyns, M., Appl. Phys. Lett. 80, 1975 (2002).Google Scholar
10. Gavartin, J. L., Munoz-Ramo, D., Shluger, A. L., and Bersuker, G., SEMATECH 2nd International Workshop on Advanced Gate Stacks Technology, p. 56 (2005).Google Scholar
11. Ribes, G., Bruyere, S., Roy, D., Parthasarthy, C., Muller, M., Denais, M., Huard, V., Skotnicki, T., and Ghibaudo, G., IEEE IIRW, p. 75 (2005).Google Scholar
12. Houssa, M, High-k Gate Diectrics, IOP Publishing, Bristol and Philadelphia (2004).Google Scholar
13. Chowdhury, N.A., Bersuker, G., Young, C., Choi, R., Krishnan, S., Misra, D., Microelectronics Engg. 85, 27 (2008).Google Scholar
14. Southwick, R. G., Reed, J., Buu, C., Butler, R., Bersuker, G., and Knowlton, W. B., IEEE Trans. Device Mater. Reliab. 10, 201 (2010).Google Scholar
15. Li, Ling, Meller, Gregor, and Kosina, Hans, Solid State Electronics 51, 445 (2007).Google Scholar