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High Frequency Capacitance Measurements On Metal-Insulator-Semiconductor Structures In Thermal Non-Equilibrium Condition

Published online by Cambridge University Press:  10 February 2011

M. Sadeghi
Affiliation:
Department of Solid State Electronics, Chalmers University of Technology, S–412 96 Göteborg, Sweden
A. Jauhiainen
Affiliation:
Department of Solid State Electronics, Chalmers University of Technology, S–412 96 Göteborg, Sweden
B. Liss
Affiliation:
Department of Solid State Electronics, Chalmers University of Technology, S–412 96 Göteborg, Sweden
E. Ö. Sveinbjörnsson
Affiliation:
Department of Solid State Electronics, Chalmers University of Technology, S–412 96 Göteborg, Sweden
O. Engström
Affiliation:
Department of Solid State Electronics, Chalmers University of Technology, S–412 96 Göteborg, Sweden
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Abstract

We simulate the charge carrier traffic between the energy bands and the interface states in structures like Al/SiO2/6H-SiC, Al/diamond/Si and Al/SIPOS/Si to explain their high frequency capacitance-voltage behavior. The structures have in common that traditional electrical measurement techniques performed at room temperature are strongly influenced by non-equilibrium carrier conditions at the insulator-semiconductor interface. This can result in large errors in the interface data extracted from such studies when thermal equilibrium conditions are assumed. In this work, high frequency capacitance-voltage data are compared to numerical simulations which include such thermal non-equilibrium conditions to enable more accurate estimates of interface state parameters in such structures.

Type
Research Article
Copyright
Copyright © Materials Research Society 1998

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References

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