A Ferroelectric NAND Flash Memory for Low-power and Highly Reliable Enterprise SSDs and a Ferroelectric 6T-SRAM for 0.5V Low-power CPU and SoC

Abstract

This paper overview recent research results about ferroelectric FETs such as a Ferroelectric (Fe-) NAND flash memory for enterprise SSDs and a Ferroelectric 6T-SRAM for 0.5V operation low-power CPU and SoC.

In the last five years, as the data through internet increases, the power consumption at the data center doubled. To solve the power crisis SSD is expected to replace HDD. For such an enterprise SSD, the Fe-NAND flash memory is most suitable due to a low power consumption and a high reliability. The Fe-NAND is composed of Metal Ferroelectric Insulator Semiconductor transistors. The program/erase voltage decreases from 20V to 6V. In the Fe-NAND, the electric polarization in the ferroelectric layer flips with a lower electric field and the V_th of a memory cell shifts. Due to a low program/erase voltage, a low power operation is achieved. In the Fe-NAND, a high write/erase endurance, 100Million cycle, four orders of magnitudes higher than the conventional NAND, is realized because there is no stress-induced leakage current.

The Fe-NAND flash memory with a non-volatile (NV) page buffer is also proposed. The data fragmentation of SSD in a random write is removed by introducing a batch write algorithm. As a result, the SSD performance can double. The NV-page buffer realizes a power outage immune highly reliable operation. In addition, a zero V_th memory cell scheme is proposed to best optimize the reliability of the Fe-NAND. The V_th shift caused by the read disturb, program disturb and data retention decreases by 32%, 24% and 10%, respectively. A 1.2V operation adaptive charge pump circuit for the low voltage and low power Fe-NAND is introduced. By using Fe-FETs as diodes in the charge pump and optimizing the V_th of Fe-FETs at each pump stage, the power efficiency and the output voltage increase by 143% and 25% without the circuit area and process step penalty.

Finally, a ferroelectric 6T-SRAM is proposed for the 0.5V operation low power CPU and SoC. During the read/hold, the V_th of Fe-FETs automatically changes to increase the static noise margin by 60%. During the stand-by, the V_th increases to decrease the leakage current by 42%. As a result, the supply voltage by 0.11V, which decreases the active power by 32%.