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Fabrication and Evaluation of 3D Packages with Through Hole Via

Published online by Cambridge University Press:  26 February 2011

Dong Min Jang ,
Kwang Yong Lee ,
Chung Hyun Ryu ,
Byeong Hoon Cho ,
Tae Sung Oh ,
Joung Ho Kim ,
Won Jong Lee  and
Jin Yu
Dong Min Jang
Affiliation:
[email protected], KAIST, MS&E, Yusunggu Gusungdong 373-1, Daejeon, 305-701, Korea, Republic of, 82-42-869-4274, 82-42-869-8840
Kwang Yong Lee
Affiliation:
[email protected], Hongik University, CEPM, Mapogu Sangsudong 72-1, Seoul, 121-791, Korea, Republic of
Chung Hyun Ryu
Affiliation:
[email protected], KAIST, CEPM, Yusunggu Gusungdong 373-1, Daejeon, 305-701, Korea, Republic of
Byeong Hoon Cho
Affiliation:
[email protected], KAIST, CEPM, Yusunggu Gusungdong 373-1, Daejeon, 305-701, Korea, Republic of
Tae Sung Oh
Affiliation:
[email protected], Hongik University, CEPM, Mapogu Sangsudong 72-1, Seoul, 121-791, Korea, Republic of
Joung Ho Kim
Affiliation:
[email protected], KAIST, CEPM, Yusunggu Gusungdong 373-1, Daejeon, 305-701, Korea, Republic of
Won Jong Lee
Affiliation:
[email protected], KAIST, CEPM, Yusunggu Gusungdong 373-1, Daejeon, 305-701, Korea, Republic of
Jin Yu
Affiliation:
[email protected], KAIST, CEPM, Yusunggu Gusungdong 373-1, Daejeon, 305-701, Korea, Republic of
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Abstract

System in package (SiP) is a superb candidate to enhance the area efficiency and performance of electronic packaging. Here, recent work on stacked chip type 3D SiP with vertically interconnected through hole vias are reported. The process includes; formation of 50um-diameter via holes, conformal deposition of SiO2 dielectric layer, deposition of Ta and Cu barrier layers, via filling by Cu electroplating, Cu/Sn bump formation for multi-chip stacking, and finally chip-to-PCB bonding using Sn-3.0Ag-0.5Cu solder and ENIG pad. A prototype 3D SiP stacked up to 10 layers was successfully fabricated.

A high frequency electrical model of the through hole via was proposed and the model parameters were extracted from measured S-parameters. The proposed model was verified by TDR/TDT (time domain reflectometry/time domain transmission) and eye-diagram measurement. Contact resistances of Cu via and bump joint were presented.

Keywords

electrical propertieselectrodepositionpackaging
Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 970: Symposium Y – Enabling Technologies for 3-D Integration , 2006 , 0970-Y05-06
Copyright
Copyright © Materials Research Society 2007

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References

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