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Evaluating Oxide Liner and Copper Barrier Integrity of Through-Silicon-Via by Electrical Characterization and Microanalysis

Published online by Cambridge University Press:  05 June 2013

Minrui Yu ,
Bharat Bhushan ,
Niranjan Kumar ,
Mun Kyu Park ,
John Hua ,
Shwetha Bolagond ,
Anthony C-T. Chan ,
Miao Jin ,
Yuri Uritsky  and
Chin-hock Toh
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Minrui Yu
Affiliation:
Silicon Systems Group, Applied Materials Inc., 974 E. Arques Ave., Sunnyvale, CA, 94085, United States
Bharat Bhushan
Affiliation:
Asia Product Development Center, Applied Materials Inc., 10 Science Park Rd., The Alpha Singapore Science Park II, 117684, Singapore
Niranjan Kumar
Affiliation:
Silicon Systems Group, Applied Materials Inc., 974 E. Arques Ave., Sunnyvale, CA, 94085, United States
Mun Kyu Park
Affiliation:
Silicon Systems Group, Applied Materials Inc., 974 E. Arques Ave., Sunnyvale, CA, 94085, United States
John Hua
Affiliation:
Silicon Systems Group, Applied Materials Inc., 974 E. Arques Ave., Sunnyvale, CA, 94085, United States
Shwetha Bolagond
Affiliation:
Silicon Systems Group, Applied Materials Inc., 974 E. Arques Ave., Sunnyvale, CA, 94085, United States
Anthony C-T. Chan
Affiliation:
Silicon Systems Group, Applied Materials Inc., 974 E. Arques Ave., Sunnyvale, CA, 94085, United States
Miao Jin
Affiliation:
Silicon Systems Group, Applied Materials Inc., 974 E. Arques Ave., Sunnyvale, CA, 94085, United States
Yuri Uritsky
Affiliation:
Silicon Systems Group, Applied Materials Inc., 974 E. Arques Ave., Sunnyvale, CA, 94085, United States
Chin-hock Toh
Affiliation:
Asia Product Development Center, Applied Materials Inc., 10 Science Park Rd., The Alpha Singapore Science Park II, 117684, Singapore
Arvind Sundarrajan
Affiliation:
Asia Product Development Center, Applied Materials Inc., 10 Science Park Rd., The Alpha Singapore Science Park II, 117684, Singapore
John Dukovic
Affiliation:
Silicon Systems Group, Applied Materials Inc., 974 E. Arques Ave., Sunnyvale, CA, 94085, United States
Sesh Ramaswami
Affiliation:
Silicon Systems Group, Applied Materials Inc., 974 E. Arques Ave., Sunnyvale, CA, 94085, United States
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Abstract

3D integration enabled by through-silicon-via (TSV) allows continued performance enhancement and power reduction for semiconductor devices, even without further scaling. For TSV wafers with all Applied Materials unit processes, we evaluate the integrity of oxide liner and copper barrier by capacitance-voltage (C-V) and current-voltage (I-V) measurements, from which oxide capacitance, minimum TSV capacitance, and leakage current are extracted. The capacitance values match well with model predictions. The leakage data also demonstrate good wafer-scale uniformity. The liner and barrier quality are further verified with microanalysis techniques.

Keywords

packagingelectrical propertiesdielectric
Type
Articles
Information
MRS Online Proceedings Library (OPL) , Volume 1559: Symposium AA – Advanced Interconnects for Micro- and Nanoelectronics—Materials, Processes and Reliability , 2013 , mrss13-1559-aa08-04
Copyright
Copyright © Materials Research Society 2013 

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References

REFERENCES

Wu, B., Kumar, A., and Ramaswami, S., “3D IC Stacking Technology, ” pp. 477, McGraw-Hill, 2011.Google Scholar
Li, Y., et al. ., “Electrical Characterization Method to Study Barrier Integrity in 3D Through-Silicon Vias, ” IEEE 62nd ECTC, pp. 304, San Diego, California, June 2012.Google Scholar
Yu, M., Dukovic, J., Bhushan, B., Kumar, N., and Ramaswami, S., Nanochip, 11, 20 (2013).Google Scholar
Kumar, N., Ramaswami, S., Dukovic, J., Tseng, J., Ding, R., Rajagopalan, N., Eaton, B., Mishra, R., Yalamanchili, R., Wang, Z., Xia, S., Sapre, K., Hua, J., Chan, A., Mori, G., and Linke, B., 2012 Electron. Compon. Technol. Conference, pp. 787, Las Vegas, Nevada, May 2012.Google Scholar
Stucchi, M., Velenis, D., and Katti, G., IEEE Trans. Instrum. Meas., 61, 1979 (2012).CrossRefGoogle Scholar
Katti, G., Stucchi, M., Velenis, D., Sorée, B., De Meyer, K., and Dehaene, W., IEEE. Device Lett., 32, 563 (2011).CrossRefGoogle Scholar
Stucchi, M., Perry, D., Katti, G., Dehaene, W., and Velenis, D., IEEE Trans. Semicond. Manuf., 25, 355 (2012).CrossRefGoogle Scholar