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Etch Process Optimization and Electrical Improvement in TiN Hard Mask Ultra-Low K Interconnection

Published online by Cambridge University Press:  30 July 2012

Chih-Yang Chang ,
Sean Kang ,
Chia-ling Kao ,
Bhargav S. Citla ,
Nikos Bekiaris ,
Yongmei Chen ,
Lothar Chan-Sew  and
Thorsten Lill
Chih-Yang Chang*
Affiliation:
SSG/ETCH, Applied Materials, 974 E Arques Ave., Sunnyvale, CA 94085 U.S.A.
Sean Kang
Affiliation:
SSG/ETCH, Applied Materials, 974 E Arques Ave., Sunnyvale, CA 94085 U.S.A.
Chia-ling Kao
Affiliation:
SSG/ETCH, Applied Materials, 974 E Arques Ave., Sunnyvale, CA 94085 U.S.A.
Bhargav S. Citla
Affiliation:
SSG/CTO Department, Applied Materials, 974 E Arques Ave., Sunnyvale, CA 94085 U.S.A.
Nikos Bekiaris
Affiliation:
SSG/CTO Department, Applied Materials, 974 E Arques Ave., Sunnyvale, CA 94085 U.S.A.
Yongmei Chen
Affiliation:
SSG/CTO Department, Applied Materials, 974 E Arques Ave., Sunnyvale, CA 94085 U.S.A.
Lothar Chan-Sew
Affiliation:
SSG/ETCH, Applied Materials, 974 E Arques Ave., Sunnyvale, CA 94085 U.S.A.
Thorsten Lill
Affiliation:
SSG/ETCH, Applied Materials, 974 E Arques Ave., Sunnyvale, CA 94085 U.S.A.
*
*Corresponding author. Tel: +1-408-584-0582; E-mail: [email protected]
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Abstract

As critical dimensions decrease, key dimension-related dielectric etch challenges emerge, including via and trench uniformity and etch depth profile. The transition to ultra-low-k films such as BDIII (Black Diamond; k=2.55) dielectrics requires consideration of film sensitivity to compositional modification, polymer interactions at pores, and the effect of diffusion. Use of N2/O2 plasma at 60 ˚C to modify the M1 trench profile has been demonstrated to lower the RC delay by 14% as compared to traditional CO2 plasmas at 60˚C. Use of a DHF solution to clean the etching residue in the dual damascene structure results in >97% yield with a tight range of via chain resistance.

Keywords

dielectricchemical reactionplasma deposition
Type
Articles
Information
MRS Online Proceedings Library (OPL) , Volume 1428: Symposium C – Interconnect Challenges for CMOS Technology—Materials, Processes and Reliability for Downscaling, Packaging and 3D Stacking , 2012 , mrss12-1428-c07-04
Copyright
Copyright © Materials Research Society 2012

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References

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