Hostname: page-component-586b7cd67f-r5fsc Total loading time: 0 Render date: 2024-11-28T04:27:02.220Z Has data issue: false hasContentIssue false
  • English
  • Français

Epitaxial and Non-Epitaxial Heterogeneous Integration Technologies at NGST

Published online by Cambridge University Press:  01 February 2011

Augusto Gutierrez-Aitken ,
Patty Chang-Chien ,
Bert Oyama ,
Kelly Tornquist ,
Khanh Thai ,
Dennis Scott ,
Rajinder Sandhu ,
Joe Zhou ,
Peter Nam  and
Wen Phan
Augusto Gutierrez-Aitken
Affiliation:
[email protected], Northrop Grumman Space Technology, Microelectronics, One Space Park, Redondo Beach, CA, 90278, United States
Patty Chang-Chien
Affiliation:
[email protected], Northrop Grumman Space Technology, Redondo Beach, CA, 90278, United States
Bert Oyama
Affiliation:
[email protected], Northrop Grumman Space Technology, Redondo Beach, CA, 90278, United States
Kelly Tornquist
Affiliation:
[email protected], Northrop Grumman Space Technology, Redondo Beach, CA, 90278, United States
Khanh Thai
Affiliation:
[email protected], Northrop Grumman Space Technology, Redondo Beach, CA, 90278, United States
Dennis Scott
Affiliation:
[email protected], Northrop Grumman Space Technology, Redondo Beach, CA, 90278, United States
Rajinder Sandhu
Affiliation:
[email protected], Northrop Grumman Space Technology, Redondo Beach, CA, 90278, United States
Joe Zhou
Affiliation:
[email protected], Northrop Grumman Space Technology, Redondo Beach, CA, 90278, United States
Peter Nam
Affiliation:
[email protected], Northrop Grumman Space Technology, Redondo Beach, CA, 90278, United States
Wen Phan
Affiliation:
[email protected], Northrop Grumman Space Technology, Redondo Beach, CA, 90278, United States
Get access

Abstract

To meet increasingly challenging and complex systems requirements, it is not enough to use one single semiconductor technology but to integrate several high performance technologies in an efficient and cost effective way. Heterogeneous integration (HI) approaches lead to a significant higher design flexibility and performance. In this paper we present some of the HI approaches that are being used and developed at Northrop Grumman Space Technology (NGST) that include selective epitaxial growth, metamorphic growth and wafer level packaging (WLP) technology. More recently we are developing a scaled and selective wafer packaging technique to integrate III-V semiconductors with silicon under the COSMOS DARPA program.

Keywords

devicesIII-Vmicroelectronics
Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 1068: Symposium C – Advances in GaN, GaAs, SiC and Related Alloys on Silicon Substrates , 2008 , 1068-C02-02
Copyright
Copyright © Materials Research Society 2008

Access options

Get access to the full version of this content by using one of the access options below. (Log in options will check for institutional or personal access. Content may require purchase if you do not have access.)

References

REFERENCES

[1] Tsai, R. Barsky, M. Boos, J. B. Bennett, B. R. Lee, J. Magno, R. Namba, C. Liu, P. H. Park, D. Grundbacher, R. and Gutierrez, A. “Metamorphic AlSb/InAs HEMT for Low-Power, High-Speed Electronics”, 2003 GaAs Integrated-Circuit Symposium, San Diego, CA. Google Scholar
[2] Deal, W.R. Tsai, R. Lange, M.D. Boos, J.B. Bennett, B.R. Gutierrez, A. “A Low Power/Low Noise MMIC Amplifier for Phased-Array Applications using InAs/AlSb HEMT,” in Microwave Symposium Digest, 2006. IEEE MTT-S International, pp 2051–2054, June 2006 Google Scholar
[3] Deal, W.R. Tsai, R. Lange, M.D. Boos, J.B. Bennett, B.R. and Gutierrez, A. “A W-band InAs/AlSb low-noise/low-power amplifier,” IEEE Microwave and Wireless Components Letters, Volume 15, Issue 4, pp 208–210, April 2005.Google Scholar
[4] Monier, C. Cavus, A. Sandhu, R.S. Oshiro, A. Li, D. Matheson, D. Chan, B. and Gutierrez-Aitken, A., “Low Power High-Speed Circuits with InAs-based HBT Technology,” Presented at the 2006 Imitational Conference on Compound Semiconductor Manufacturing Technology, April 24-27, 2006, Vancouver, Canada.Google Scholar
[5] Chang-Chien, P., Zeng, P. X. Tornquist, K. Nishimoto, M. Battung, M. Chung, Y. Yang, J. Farkas, D. Yajima, M. Cheung, C. Luo, K. Eaves, D. Lee, J. Uyeda, J. Duan, D. Fordham, O. Chung, T. Sandhu, R. Tsai, R. “MMIC Compatible Wafer-Level Packaging Technology,” in IEEE 19th International Conference on Indium Phosphide & Related Materials, May 14-18, 2007, Matsue, Japan Google Scholar
[6] Farkas, D. Luna, T. Chang-Chien, P., Tornquist, K. Fordham, O. Tsai, R. “Demonstration of a Low Loss W-band Interconnect and Circuit Isolation Structure for Wafer Scale Assembly,” in IEEE/MTT-S International Microwave Symposium, June 3-8, 2007.Google Scholar
[7] Yang, J. Chung, Y. Nishimoto, M. Battung, M. Long, A. Chang-Chien, P., Tornquist, K. Siddiqui, M. Lai, R. “Wafer Level Integrated Antenna Front End Module For Low Cost Phased Array Implementation,” in IEEE/MTT-S International Microwave Symposium, June 3-8, 2007.Google Scholar