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Effects of Inversion Layer Quantization and Polysilicon Gate Depletion on Tunneling Current of Ultra-Thin SiO2 Gate Material

Published online by Cambridge University Press:  10 February 2011

S. Saha ,
G. Srinivasan ,
G. A. Rezvani  and
M. Farr
S. Saha
Affiliation:
Technology Development, VLSI Technology, Inc., San Jose, CA 95131, [email protected]
G. Srinivasan
Affiliation:
Technology Development, VLSI Technology, Inc., San Jose, CA 95131, [email protected]
G. A. Rezvani
Affiliation:
Technology Development, VLSI Technology, Inc., San Jose, CA 95131, [email protected]
M. Farr
Affiliation:
Technology Development, VLSI Technology, Inc., San Jose, CA 95131, [email protected]
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Abstract

We have investigated the impact of inversion layer quantization and polysilicon-gate depletion effects on the direct-tunneling gate-leakage current and reliability of ultra-thin silicon-dioxide gate dielectric. The gate-leakage current was measured for nMOSFET devices with gate oxide thickness down to 3 nm. A simulation-based methodology was used to determine the physical oxide thickness from the measured capacitance data, and the corresponding effective gate oxide thickness at inversion was computed from the simulation data obtained with and without the quantum mechanical and polysilicon depletion effects. The simulation results indicate that the effective gate oxide thickness is significantly higher than the physically grown oxide thickness due to inversion layer quantization and polysilicon depletion effects. The increase in oxide thickness is strongly dependent on the supply voltage and is more than 0.6 nm at 1 V. Our data, also, show that in order to maintain a leakage current ≥ 1 A/cm2 for 1 V operation, the effective gate oxide thickness must be ≥ 2.2 nm.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 567: Symposium R – Ultrathin SiO2 and Higg-K Materials for ULSI Gate Dielectrics , 1999 , 275
Copyright
Copyright © Materials Research Society 1999

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References

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