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Copper Migration During Tungsten via Formation

Published online by Cambridge University Press:  01 February 2011

Jeff Gambino ,
Ed Cooney ,
Will Murphy ,
Cameron Luce ,
Steve Mongeon ,
Ning Lai ,
Bob Zwonik ,
Felix Anderson ,
Laura Schutz  and
Tom C Lee
...Show all authors
Jeff Gambino
Affiliation:
[email protected], IBM, 1000 River Street, Z/975A, Essex Junction, Vermont, 05452, United States
Ed Cooney
Affiliation:
[email protected], IBM, Essex Junction, Vermont, United States
Will Murphy
Affiliation:
[email protected], IBM, Essex Junction, Vermont, United States
Cameron Luce
Affiliation:
[email protected], IBM, Essex Junction, Vermont, United States
Steve Mongeon
Affiliation:
[email protected], IBM, Essex Junction, Vermont, United States
Ning Lai
Affiliation:
[email protected], IBM, Essex Junction, Vermont, United States
Bob Zwonik
Affiliation:
[email protected], IBM, Essex Junction, Vermont, United States
Felix Anderson
Affiliation:
[email protected], IBM, Essex Junction, Vermont, United States
Laura Schutz
Affiliation:
[email protected], IBM, Essex Junction, Vermont, United States
Tom C Lee
Affiliation:
[email protected], IBM, Essex Junction, Vermont, United States
Tom McDevitt
Affiliation:
[email protected], IBM, Essex Junction, Vermont, United States
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Abstract

A yield problem is observed with tungsten vias formed on copper interconnects. Copper migration can occur during chemical vapor deposition (CVD) of tungsten, if there are defects in the liner inside the via. Copper can react quickly with SiH4 during the early stages of tungsten deposition, when SiH4-reduction of WF6 is used. Under severe conditions, large amounts of copper diffuse out of the underlying metal layer, resulting in copper silicide formation in the via and leaving voids in the copper wire. Copper migration can be minimized by reducing the time that the wafers are exposed to SiH4.

Keywords

CumicroelectronicsW
Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 1249: Symposia E/F – Advanced Interconnects and Chemical Mechanical Planarization for Micro-and Nanoelectronics , 2010 , 1249-F01-08
Copyright
Copyright © Materials Research Society 2010

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