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Buried Oxide Soi: Materials, Devices, and VLSI Circuits

Published online by Cambridge University Press:  28 February 2011

C.-E. Daniel Chen  and
Rad-Hard Soi Project Team
C.-E. Daniel Chen
Affiliation:
Semiconductor Process and Design Center, Texas Instruments, Inc. MS 944, P. O. Box 655621, Dallas,TX 75265.
Rad-Hard Soi Project Team
Affiliation:
Semiconductor Process and Design Center, Texas Instruments, Inc. MS 944, P. O. Box 655621, Dallas,TX 75265.
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Abstract

In the past couple of years, buried oxide SOI has emerged as the leading SOI approach. Significant advances have been made in the understanding and the preparation of the buried oxide substrates. Various VLSI circuits have been demonstrated with excellent results, proving the maturity and the manufacturability of this technology. In this paper, buried oxide material properties, device parameters and the implementation of a 2.5 urn 4K SRAM and a 1.25 pm 16K SRAM on the buried oxide substrates are reviewed.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 107: Symposium H – Silicon-on-Insulator and Buried Metals in Semiconductors , 1987 , 309
Copyright
Copyright © Materials Research Society 1988

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References

1 Chen, C.-E. and Chatterjee, P., presented at the 34th National Symposium of the American Vacuum Society, Anaheim, CA, November, 1987, and to be published in Deposition and Growth: Limits for Microelectronics, edited by G. W. Rubloff (AIP Conference Proceeding, American Vacuum Society Series)Google Scholar
2 Chen, C.-E., Blake, T.G.W., Hite, L.R., Malhi, S.D.S., Mao, B.-Y., and Lam, H.W., IEDM Technical Digest, 702(1984)Google Scholar
3 Chen, C.-E., Matloubian, M., Mao, B.-Y., Sundaresan, R., Slawinski, C., Lam, H.W., Blake, T.G.W., Hite, L.R., and Hester, R. K., IEEE Trans. Elect. Dev., ED-33. 1840(1986)CrossRefGoogle Scholar
4 Mao, B.-Y., Chang, P.-H., Lam, H. W., Shen, B. W., and Keenan, J. A., Appl. Phys. Lett.,48, 794(1986)Google Scholar
5 Izumi, K., Ooken, M., and Ariyoshi, H., Electron Lett., vol 14, 593(1978)Google Scholar
6 Izumi, K., Omura, Y., Ishikawa, M., and Sano, E., Symposium on VLSI Technology Dig. 10 (1982)Google Scholar
7 Omura, Y., Nakashima, S., and Izumi, K., Symposium on VLSI Technology Dig. 24 (1985)Google Scholar
8 Hashimoto, K., Kamins, T. I., Cham, K. M., and Chang, S. Y., IEDM Tech. Dig., 672(1985)Google Scholar
9 Colinge, J.-P., IEEE Trans. Elect. Dev., ED-34. 2173(1987)CrossRefGoogle Scholar
10 Jaussaud, C., Stoemenos, J., Margail, J., Dupuy, M., Blenchard, B., and Bruel, M., Appl. Phys. Lett.,46, 1064(1985)Google Scholar
11 Mao, B.-Y., Matloubian, M., Chen, C.-E., Sundaresan, R., and Slawinski, C., IEEE Elect. Dev. Lett., EDL-8. 306(1987)Google Scholar
12 Mao, B.-Y., Chang, P.-H., Chen, C.-E., and Lam, H.W., J. Appl. Phys., 62, 2308(1987)Google Scholar
13 Chang, P.-H., Slawinski, C., Mao, B.-Y., and Lam, H. W., J. Appl. Phys., 61, 166(1987)Google Scholar
14 Mao, B.-Y., Chen, C.-E., Pollack, G., Hughes, H. L., and Davis, G. E., to be published in the December, 1987 issue of IEEE Trans. Nucl. Sci. Google Scholar
15 Hill, D., Fraundorf, P., and Fraundorf, G., to be published in J. Appl. Phys. Also, this work has been repeated, and expanded at Texas Instruments.Google Scholar
16 Margail, J., LETI (private communication).Google Scholar
17 Mao, B.-Y., Chen, C.-E., Matloubian, M., Hite, L. R., Pollack, G., Hughes, H. L., and Maley, K., IEEE Trans. Nucl. Sci.,33, 1702(1986)CrossRefGoogle Scholar
18 Davis, G. E., Hite, L. R., Blake, T. G. W., Chen, C.-E., and Lam, H. W., IEEE Trans. Nucl. Sci., vol. NS-32. 4432(1985)Google Scholar