Analysis of Copper and Low-K Dielectric Interconnect System for 0.18-μm Technology

Abstract

As the interconnect RC delay plays an increasingly dominant role in the performance of deep submicron ULSI devices, Cu and low-k dielectric materials are deemed necessary to replace the traditional Al and SiO₂ system to lower both the resistance and capacitance of metallization. This paper presents a systematic simulation method to assess the impact of Cu and low-k dielectric to the system speed and cross-talk noise for 0.18-μm design rules (0.6 μm pitch), and determine the practical process windows for metal line aspect ratio and the structural configuration of dielectrics. It was found that the high performance requirements for 0.18-μm devices (600 MHz and cross-talk <0.3 on a 2×2 cm² chip) cannot be met by simply replacing Al with Cu or SiO₂ with low-k dielectric (k=3), without any change in the interconnect architecture. By reverse scaling the metal pitch to 2× at upper levels, on the other hand, one can easily find a manufacturable process window, even with the Al and SiO₂ system. Case studies on R and C of various structural configurations and boundary conditions have been performed, including Cu barrier layer thickness, metal gap fill and capping layer thickness of low-k dielectrics, as well as the influence of the lower and upper metal plates. The significance of the results on the strategy of implementing Cu/low-k interconnects versus extending Al/SiO₂ will be discussed.