Hostname: page-component-cd9895bd7-8ctnn Total loading time: 0 Render date: 2024-12-29T12:04:22.067Z Has data issue: false hasContentIssue false
  • English
  • Français

3D Process Integration – Requirements and Challenges

Published online by Cambridge University Press:  01 February 2011

Juergen Max Wolf ,
Armin Klumpp ,
Kai Zoschke ,
Robert Wieland ,
Lars Nebrich ,
Matthias Klein ,
Hermann Oppermann ,
Peter Ramm ,
Oswin Ehrmann  and
Herbert Reichl
Juergen Max Wolf
Affiliation:
[email protected], Fraunhofer IZM, Germany
Armin Klumpp
Affiliation:
[email protected], Fraunhofer IZM, München, Germany
Kai Zoschke
Affiliation:
[email protected], Fraunhofer IZM, Germany
Robert Wieland
Affiliation:
[email protected], Fraunhofer IZM, Germany
Lars Nebrich
Affiliation:
[email protected], Fraunhofer IZM, Germany
Matthias Klein
Affiliation:
[email protected], Fraunhofer IZM, Germany
Hermann Oppermann
Affiliation:
[email protected], Fraunhofer IZM, Germany
Peter Ramm
Affiliation:
[email protected], Fraunhofer IZM, Germany
Oswin Ehrmann
Affiliation:
[email protected], Fraunhofer IZM, Germany
Herbert Reichl
Affiliation:
[email protected], Fraunhofer IZM, Germany
Get access

Abstract

Heterogeneous system integration is one of the key topics for future system integration. Scaling of System on Chip (SoC) alone does not address today's requirements of smart electronic systems in terms of performance, functionality, miniaturization, low production cost and time to market. The traditional microelectronic packaging will more and more convert into complex sys-tem integration. ‘More than Moore’ will be required due to tighter integration of system level components at the package level. This trend leads to advanced System in Package solutions (SiP) which require the synergy and a combination of wafer level and board integration technologies and which are rapidly evolving from a specialty technology used in a narrow set of applications to a high volume technology with wide ranging impact on electronics markets especially due to the high volume and very cost competitive consumer and communication market. Advanced SiP approaches explore the third dimension which results in complex system architectures that also require, beside new technologies and improved materials, adequate system design tools and reli-ability models. One of the most promising technology approaches is 3D packaging which in-volves a set of different integration approaches including stacked packages, silicon interposer with Through Silicon Vias (TSV) and embedding technologies. The paper highlights future sys-tem and potential technical solutions.

Keywords

thin filmelectrodepositionpackaging
Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 1112: Symposium E – Materials and Technologies for 3-D Integration , 2008 , 1112-E01-01
Copyright
Copyright © Materials Research Society 2009

Access options

Get access to the full version of this content by using one of the access options below. (Log in options will check for institutional or personal access. Content may require purchase if you do not have access.)

References

REFERENCES

1. ENIAC, ITRS 2006/2007 Google Scholar
2. Assembly &Packaging Roadmap ITRS, 2007/2008, white paper: System in Package - SiP, Semi, USA; http:\\www.itrs.net/Links/2007ITRS/LinkedFiles/AP/AP_Paper.pdf Google Scholar
3. Reichl, H; Wolf, M. J. “Hetero System Integration Challenges and Requirements for Packaging”, MHSI 2006, Sendai, Japan, 6.–7. November 2006.Google Scholar
4. Reichl, H.; Wolf, M. J., “Potential Technologies for Wireless Sensor Nodes”, Nano-Manufacturing Technology Pioneering Life Science for Health, Tokyo, Japan 2006.Google Scholar
5. Reichl, H., “Systems Integration – Requirements and Technical Solutions”, 2007 IEEE European Systems Packaging Workshop, Como, Italy, Jan. 2007.Google Scholar
6. Wolf, M.J.; Reichl, H., “The eGrain / e-Cube Concept” EWSN 2006, Feb. 13–15 2006, Zurich, Switzerland.Google Scholar
7. Ramm, P. and Sauer, A., ‘3D integration technologies for ultrasmall wireless sensor systems – the e-CUBES project’, Future Fab International, Issue 23 (2007) 80–82,Google Scholar
8. http:\\www.ecubes.org Google Scholar
9. Utsunomiya, H., “Packaging Substrate technologies trend in Japan” Proc. Pan Pacific 2008, Jan. 22.–24. 2008, Kauai, Hawaii (USA).Google Scholar
10. Boettcher, L., Manessis, D., Neumann, A., Ostmann, A., Reichl, H., “Chip embedding by Chip in Polymer technology”, Proceedings Device Packaging Conference 2007, Scottsdale, Arizona (USA).Google Scholar
11. Reichl, H., “Potentiale der Leiterplatte für die Systemintegration - Multifunktionale PCB”, Fachtagung Elektronische Baugruppen und Leiterplatten, Feb. 13. 2008, Fellbach, Germany.Google Scholar
12. Brunnbauer, M., Fürgut, E., Beer, G., Meyer, T., “Embedded Wafer Level Ball Grid Array (eWLB),” Electronics Packaging Technology Conference, EPTC 2007, Singapore, Dec. 2007.Google Scholar
13. Brunnbauer, M. and Meyer, T., “Embedded Wafer Level Ball Grid Array”, 3rd Annual Device Packaging Conference IMAPS 2008, Scottsdale (Arizona, USA), March 2008.Google Scholar
14. Zoschke, K., Reichl, H.: “Herstellung integrierter passiver Komponenten auf Wafer Ebene”, Mikrosystemtechnik Konferenz Dresden, Oct. 15.-17. 2007.Google Scholar
15. Ramm, P., “3D System Integration: Enabling Technologies and Applications”, Int. Conf. on Solid State Devices and Materials SSDM 2006, Yokohama (2006) 318–319.Google Scholar
16. Ramm, P. and Buchner, R., “Method of making a vertically integrated circuit”, US Patent 5,766,984, Sep. 22, 1994.Google Scholar
17. Wolf, M. J., Reichl, H., “3D wafer level System integration” IMAPS, Korea, Sep. 3.–4. 2008, Seoul, Korea.Google Scholar
18. Ramm, P., Wolf, M.J., Wunderle, B., “Wafer-Level 3D System Integration”. In “Handbook of 3D Integration”, Vol. 2, p. 289–318, Wiley-VCH, Weinheim, 2008.Google Scholar
19. Klumpp, et al., “Chip to Wafer Stacking by using Through-Silicon Vias and Solid Liquid Interdiffusion”, 2nd Int. IEEE Workshop on 3D System integration, Munich, Germany, Oct. 1, 2007.Google Scholar
20. BMBF Project “KASS” FKZ: 01M3163A, 01M3163BGoogle Scholar
21. http://xwww.emc3d.org Google Scholar
22. Wolf, M.J., Dretschkow, T., Wunderle, B., Jürgensen, N., Engelmann, G., Ehrmann, O., Uhlig, A., Michel, B., Reichl, H., “High Aspect Ratio TSV Copper Filling with Different Seed Layers”. ECTC 2008, May 27-30, 2008, Orlando, USA.Google Scholar