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Through-silicon via stress characteristics and reliability impact on 3D integrated circuits

Published online by Cambridge University Press:  10 March 2015

Tengfei Jiang ,
Jay Im ,
Rui Huang  and
Paul S. Ho
Tengfei Jiang
Affiliation:
The University of Texas at Austin, USA; [email protected]
Jay Im
Affiliation:
The University of Texas at Austin, USA; [email protected]
Rui Huang
Affiliation:
The University of Texas at Austin, USA; [email protected]
Paul S. Ho
Affiliation:
Texas Materials Institute, The University of Texas at Austin, USA; [email protected]
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Abstract

Three-dimensional (3D) integration has emerged as a potential solution to the wiring limits imposed on chip performance, power dissipation, and packaging form factor beyond the 14 nm technology node. In 3D integrated circuits (ICs), the through-silicon via (TSV) is a critical element connecting die-to-die in the integrated stack structure. The thermal expansion mismatch between copper (Cu) vias and silicon (Si) can induce complex stresses in TSV structures to drive interfacial failure and Cu extrusion, degrading the performance and reliability of 3D interconnects. This article reviews current studies on thermal stresses and their effects on reliability of TSV structures. Recent results from measurements of stress and plasticity characteristics of Cu TSV structures are reviewed, including wafer curvature, micro-Raman spectroscopy, and synchrotron x-ray microdiffraction techniques. The effects of the Cu microstructure on stress and reliability, particularly on via extrusion and the device keep-out zone in TSV structures, are discussed. Based on the analysis of the reliability impact, we explore the potential of material and processing optimization to build reliable TSV structures for 3D ICs.

Keywords

microelectronicsthermal stressesCuSidevices
Type
Research Article
Information
MRS Bulletin , Volume 40 , Issue 3: Materials challenges in 3D IC technology , March 2015 , pp. 248 - 256
Copyright
Copyright © Materials Research Society 2015 

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