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Integration Challenges for CMP of Copper

Published online by Cambridge University Press:  31 January 2011

Rajeev Bajaj ,
Ajoy Zutshi ,
Rahul Surana ,
Mehul Naik  and
Tony Pan
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Abstract

As the minimum feature size of microelectronic devices shrinks down to 130 nm, copper has been successfully adopted into logic applications.1–3 Copper requires damascene processing, which involves etching features into a dielectric substrate, filling the features with metal, and removing any excess metal. Therefore, chemical—mechanical planarization (CMP) is a key process in the final definition of the inlaid copper wires on a circuit. A second advance in the back-end processing of copper is the changing of the dielectric from SiO2 to a Low-κ material, which allows a thicker layer of dielectric to be used. Low-k dielectric films have much lower mechanical properties than SiO2; consequently, this poses new challenges in developing integration schemes.1,3–8

Keywords

chemical–mechanical planarizationchemical–mechanical polishingCMPcopperelectroplatingintegrationlow-κ dielectric films.
Type
Research Article
Information
MRS Bulletin , Volume 27 , Issue 10: Advances in Chemical-Mechanical Planarization , October 2002 , pp. 776 - 778
Copyright
Copyright © Materials Research Society 2002

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References

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