Hostname: page-component-586b7cd67f-2plfb Total loading time: 0 Render date: 2024-11-24T07:26:29.418Z Has data issue: false hasContentIssue false
  • English
  • Français

Thin Film Characterization on Cu/SnAg Solder Interface for 3D Packaging Technologies

Published online by Cambridge University Press:  14 July 2020

Kimberly Beers ,
Andrew E. Hollowell  and
G. Bahar Basim
Kimberly Beers
Affiliation:
University of Florida, Materials Science and Engineering Department, Gainesville, FL32611 Sandia National Labs, Microsystems Integration, Albuquerque, NM87123
Andrew E. Hollowell
Affiliation:
Sandia National Labs, Microsystems Integration, Albuquerque, NM87123
G. Bahar Basim
Affiliation:
University of Florida, Materials Science and Engineering Department, Gainesville, FL32611
Get access

Abstract

Copper is a commonly used interconnect metal in microelectronic interconnects due to its exceptional electrical and thermal properties. Particularly in applications of the 2.5 and 3D integration, Cu is utilized in through-silicon-vias (TSVs) and flip chip interconnects between microelectronic chips for providing miniaturization, lower power and higher performance than current 2D packaging approaches. SnAg capped Cu pillars are a common high-density interconnect technology for flip chip bonding. For these interconnects, specific properties of the Cu surface, such as roughness and cleanliness, are an important factor in the process to ensure quality solder bumps. During electroplating, tight processing parameters must be met so that defects are avoided, and high bump uniformity is achieved. An understanding of the interactions at the solder and Cu pillar interface is needed, based on the electroplating parameters, to determine the best method for populating solder on the wafer surface. In this study, surface treatment techniques such as oxygen plasma cleaning were performed on the Cu surfaces and the SnAg plating chemistry for depositing the solder were evaluated through hull cell testing to qualitatively determine the range of current densities to investigate. It was observed that current density while plating played a large role in solder bump deposition morphology. At the higher current densities greater than 60 mA/cm2, bump height non-uniformity and dendritic growth are observed and at lower current densities, less than or equal to 60 mA/cm2, uniform, continuous bump height occurred.

Type
Articles
Information
MRS Advances , Volume 5 , Issue 37-38: Electronics and Photonics , 2020 , pp. 1929 - 1935
Check for updates
Copyright
Copyright © Materials Research Society 2020

Access options

Get access to the full version of this content by using one of the access options below. (Log in options will check for institutional or personal access. Content may require purchase if you do not have access.)

References

Song, C., Wang, Z., Chen, Q., Cai, J., Liu, L, Microelectron. Eng., 85 (10), 1952-1956, (2008).CrossRefGoogle Scholar
Miller, L. F., IBM J. of R&D, 13 (3), 239-250, (1969).CrossRefGoogle Scholar
Orii, Y. et al. , 2011 IEEE 61st ECTC, Lake Buena Vista, FL, 340-345, (2011).Google Scholar
Woertink, J., et al. , 2014 IEEE 64th ECTC, Orlando, FL, 342-347, (2014).Google Scholar
Helneder, Johann et al. , Microelectron. Eng., 82, (3-4), 581–586, (2005).CrossRefGoogle Scholar
Koh, Wei, et al. ., ICEPT-HDP 2011, (2011).Google Scholar
Asahi, N., Miyamoto, Y., Nimura, M., Mizutani, Y., and Arai, Y., 2015 3DIC, Sendai, Japan TS7.3.1-TS7.3.5, (2015).Google Scholar
Kostic, Andrew D., Lead-free Electronics Reliability - An Update. PDF, The Aerospace Corporation, Geoint Development Office, (2011). Available at: https://nepp.nasa.gov/whisker/reference/tech_papers/2011-kostic-Pb-free.pdf (accessed 22 May 2020)Google Scholar
Kim, Bioh, and Ritzdorf, Tom, J. of The ECS, 150 (9), C577–C584, (2003).Google Scholar
Yagan, R., Basim, G. B., ECS J. of Solid State Sc., Special Issue on Chemical Mechanical Planarization for sub 10-nm Technologies, 8 (5), 3118-3127, (2019).CrossRefGoogle Scholar