R. E. Stearns, J. Hartmanis, and P. M. LewisII. Hierarchies of memory limited computations. Sixth Annual Symposium on Switching Circuit Theory and Logical Design, University of Michigan, Ann Arbor, Mich., The Institute of Electrical and Electronics Engineers, Inc., New York 1965, pp. 179–190.

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R. E. Stearns, J. Hartmanis, and P. M. LewisII. Hierarchies of memory limited computations. Sixth Annual Symposium on Switching Circuit Theory and Logical Design, University of Michigan, Ann Arbor, Mich., The Institute of Electrical and Electronics Engineers, Inc., New York 1965, pp. 179–190.

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R. E. Stearns, J. Hartmanis, and P. M. LewisII. Hierarchies of memory limited computations. Sixth Annual Symposium on Switching Circuit Theory and Logical Design, University of Michigan, Ann Arbor, Mich., The Institute of Electrical and Electronics Engineers, Inc., New York 1965, pp. 179–190.

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R. E. Stearns, J. Hartmanis, and P. M. LewisII. Hierarchies of memory limited computations. Sixth Annual Symposium on Switching Circuit Theory and Logical Design, University of Michigan, Ann Arbor, Mich., The Institute of Electrical and Electronics Engineers, Inc., New York 1965, pp. 179–190.

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R. E. Stearns, J. Hartmanis, and P. M. LewisII. Hierarchies of memory limited computations. Sixth Annual Symposium on Switching Circuit Theory and Logical Design, University of Michigan, Ann Arbor, Mich., The Institute of Electrical and Electronics Engineers, Inc., New York 1965, pp. 179–190.

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