Hostname: page-component-78c5997874-ndw9j Total loading time: 0 Render date: 2024-11-07T03:19:39.822Z Has data issue: false hasContentIssue false

Interpretation of S-Curve and Tracking Error in a Delay-Lock-Loop

Published online by Cambridge University Press:  21 October 2009

E. S. Warner
Affiliation:
(University of Edinburgh)
J. D. Last
Affiliation:
(University of Wales, Bangor)

Abstract

The delay-lock-loop is a device used in direct-sequence spread-spectrum receivers to track the delay difference between two binary correlated waveforms. This short paper aims to clarify both the interpretation of the S-curve and the sign of the tracking error for such devices, especially those for navigation systems such as GPS.

Type
Research Article
Copyright
Copyright © The Royal Institute of Navigation 1995

Access options

Get access to the full version of this content by using one of the access options below. (Log in options will check for institutional or personal access. Content may require purchase if you do not have access.)

References

REFERENCES

1Spilker, J. J. (1963). Delay-lock tracking of binary signals. IRE Trans, on Space Electronics and Telemetry. Vol. SET-9, March 1963, pp. 18.CrossRefGoogle Scholar
2Gill, W. J. (1966). A comparison of binary delay-lock tracking-loop implementations. IEEE Trans, on Aerospace and Electronic Systems. Vol. AES-2, no. 4, July 1966, pp. 415–24.CrossRefGoogle Scholar
3Cahn, C. R. (1973). Spread spectrum applications and state-of-the-art equipments. AGARD Lecture Series No. 58. May 1973, pp. 55, 5111.Google Scholar
4Holmes, J. K. (1982). Coherent Spread-Spectrum Systems. John Wiley & Sons, New York.Google Scholar
5Ziemer, R. E. and Peterson, R. L. (1985). Digital Communications and Spread Spectrum Systems. Collier-Macmillan, New York.Google Scholar
6Van Dierendonck, A. J., Fenton, P. and Ford, F. (1992). Theory and performance of narrow correlator spacing in a GPS receiver. Proc. ION National Technical Meeting. San Diego, CA, 27th January 1992.Google Scholar
7De Gaudenzi, R., Luise, M. and Viola, R. (1991). Chip timing synchronization in an all-digital band-limited DS/SS System. IEEE Proc. ICC, pp. 52.2.1– 52.2.5.Google Scholar