Hostname: page-component-cd9895bd7-dk4vv Total loading time: 0 Render date: 2024-12-26T19:08:56.675Z Has data issue: false hasContentIssue false
  • English
  • Français

A new methodology for optimal RF DFT sensor design

Published online by Cambridge University Press:  03 July 2012

Conrado K. Mesadri ,
Aziz Doukkali ,
Philippe Descamps  and
Christophe Kelma
Conrado K. Mesadri
Affiliation:
LaMIPS, Laboratoire Commun CRISMAT-NXP Semiconductors-PRESTO Engineering, UMR 6508 CNRS, 6 Boulevard Maréchal Juin, Caen, France. Phone: + 33 231 456 029
Aziz Doukkali
Affiliation:
LaMIPS, Laboratoire Commun CRISMAT-NXP Semiconductors-PRESTO Engineering, UMR 6508 CNRS, 6 Boulevard Maréchal Juin, Caen, France. Phone: + 33 231 456 029
Philippe Descamps*
Affiliation:
LaMIPS, Laboratoire Commun CRISMAT-NXP Semiconductors-PRESTO Engineering, UMR 6508 CNRS, 6 Boulevard Maréchal Juin, Caen, France. Phone: + 33 231 456 029
Christophe Kelma
Affiliation:
NXP Semiconductors, 2 Esplanade Anton Philips, Campus Effiscience, Colombelles BP 20000, Caen 14096, Cedex 9, France
*
Corresponding author: P. Descamps Email: [email protected]
Get access Rights & Permissions [Opens in a new window]

Abstract

In this paper, a new methodology to compare the robustness of sensor structures employed in radiofrequency design for test (RF DFT) architectures for RF integrated circuits (ICs) is proposed. First, the yield loss and defect level of the test technique is evaluated using a statistical model of the Circuit under Test (obtained through non-parametric statistics and copula theory). Then, by carrying out the dispersion analysis of the sensor architecture, a figure of merit is established. This methodology reduces the number of iterations in the design flow of RF DFT sensors and makes it possible to evaluate process dispersion. The case study is a SiGe:C BiCMOS LNA tested by a single-probe measurement.

Keywords

RFID and sensorsWide-bandgap semiconductors devices and technologiesReliability and statistical analysis
Type
Research Papers
Information
International Journal of Microwave and Wireless Technologies , Volume 4 , Issue 5 , October 2012 , pp. 515 - 521
Copyright
Copyright © Cambridge University Press and the European Microwave Association 2012

Access options

Get access to the full version of this content by using one of the access options below. (Log in options will check for institutional or personal access. Content may require purchase if you do not have access.)

References

REFERENCES

[1]Akbay, S.S.; Haldar, A.; Chatterje, A.; Keezer, D.: Low – cost test of embedded RF/analog/mixed – signal circuits in SOP's. IEEE Trans. Adv. Packag., 27 (2) (2004), 352–363.Google Scholar
[2]Ellouz, S.; Gamand, P.; Kelma, C.; Vandewiele, B.; Allard, B.: Combining internal probing with artificial neural networks for optimal RFIC testing, In IEEE Int. Test Conf., 2006, Santa Clara, CA, 1–9.CrossRefGoogle Scholar
[3]Ramzan, R.; Dabrowski, J.: On-chip calibration of RF detectors by DC stimuli and artificial neural networks, In IEEE Radio Frequency Integrated Circuits (RFIC) Symp., 2008, Atlanta, GA, 571–574.Google Scholar
[4]Wang, Q.; Soma, M.: RF front-end system gain and linearity built-in test, In Proc. 24th IEEE VLSI Test Symp., 2006, Berkeley, CA, 233–269.Google Scholar
[5]Zhang, T.; Eisenstadt, W.R.; Fox, R.M.; Yin, Q.: Bipolar microwave RMS power detectors. IEEE J. Solid State Circuits, 41 (9) (2006), 2188–2192.Google Scholar
[6]Jonsson, F.; Olsson, H.: RF detector for on – chip amplitude measurement. Electron. Lett., 40 (20) (2004), 1239–1240.Google Scholar
[7]Voinigescu, S.P. et al. : A scalable high-frequency noise model for bipolar transistors with application to optimal transistor sizing for low-noise amplifier design. IEEE J. Solid State Circuits, 32 (9) (1997), 1430–1439.Google Scholar
[8]Liang, Q.; Niu, G.; Cressler, J.D.; Taylor, S.; Harame, D.L.: Geometry and bias current optimization SiGe HBT cascade low-noise amplifiers, In IEEE Radiofrequency Integrated Circuits (RFIC) Symp., 2002, Seattle, WA, 407–410.Google Scholar
[9]Meyer, R.G.: Low-power monolithic RF peak detector analysis. IEEE J. Solid State Circuits, 30 (1) (1995), 65–67.Google Scholar
[10]Stratigopoulos, H.G.; Tongbong, J.; Mir, S.: A general method to evaluate RF BIST techniques based on non-parametric density estimation, In IEEE Proc. Conf. on Design Automation and Test in Europe (DATA), 2008, Munich, 68–73.Google Scholar
[11]Nelsen, R.R.: A Introduction to Copulas, Springer, New-York, 2006.Google Scholar
[12]Wegener, C.; Kennedy, M.P.: Test development through defect and test escape level estimation for data converters. IEEE J. Electron. Test.: Theory Appl., 22 (1–6) (2006), 1–6.Google Scholar
[13]Sunter, S.; Nagi, N.: Test metrics for analog parametric faults, In Proc. 17th IEEE VLSI Test Symp., 1999, San Diego, CA, 226–234.Google Scholar