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Low-power 8-bit 5-GS/s digital-to-analog converter for multi-gigabit wireless transceivers

Published online by Cambridge University Press:  09 March 2012

Behnam Sedighi ,
Mahdi Khafaji  and
Johann Christoph Scheytt
Behnam Sedighi*
Affiliation:
National ICT Australia (NICTA), Department of Electrical and Electronic Engineering, University of Melbourne, VIC 3010, Australia.
Mahdi Khafaji
Affiliation:
IHP, Frankfurt (Oder) 15236, Germany.
Johann Christoph Scheytt
Affiliation:
IHP, Frankfurt (Oder) 15236, Germany.
*
Corresponding author: B. Sedighi[email protected]
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Abstract

We present a method to realize a low-power and high-speed digital-to-analog converter (DAC) for system-on-chip applications. The new method is a combination of binary-weighted current cells and R-2R ladder and is specially suited for modern BiCMOS technologies. A prototype 5 GS/s DAC is implemented in 0.13 μm SiGe BiCMOS technology. The DAC dissipates 26 mW and provides an SFDR higher than 48 dB for output frequencies up to 1 GHz.

Keywords

Circuit Design and ApplicationsModellingSimulation and characterizations of devices and circuits
Type
Research Papers
Information
International Journal of Microwave and Wireless Technologies , Volume 4 , Special Issue 3: European Microwave Week 2011 , June 2012 , pp. 275 - 282
Copyright
Copyright © Cambridge University Press and the European Microwave Association 2012

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