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Optimization of a 61.44 GHz BiCMOS HBT integrated PLL for ultra-fast settling time

Published online by Cambridge University Press:  16 February 2012

Atheer Barghouthi ,
Marcu Hellfeld ,
Corrado Carta  and
Frank Ellinger
Atheer Barghouthi
Affiliation:
Chair for Circuit Design and Network Theory, Dresden University of Technology, Helmholzstrasse 18, 01069, Dresden, Germany. Phone: +49 351 463 32702
Marcu Hellfeld
Affiliation:
Chair for Circuit Design and Network Theory, Dresden University of Technology, Helmholzstrasse 18, 01069, Dresden, Germany. Phone: +49 351 463 32702
Corrado Carta
Affiliation:
Chair for Circuit Design and Network Theory, Dresden University of Technology, Helmholzstrasse 18, 01069, Dresden, Germany. Phone: +49 351 463 32702
Frank Ellinger*
Affiliation:
Chair for Circuit Design and Network Theory, Dresden University of Technology, Helmholzstrasse 18, 01069, Dresden, Germany. Phone: +49 351 463 32702
*
Corresponding author: F. Ellinger Email: [email protected]
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Abstract

The design of a 61.44 GHz integrated Phase-locked loop (PLL) on a 180 GHz BiCMOS technology is presented. The PLL was optimized for a very fast settling time of 4 µs as required by the system specifications. Because the receiver is using a carrier recovery circuit that can follow the slow changes of the carrier such as phase noise, the sensitivity of the bit error rate to phase noise at the receiver end is very low. As a result, to achieve the required dynamic behavior, the phase noise performance could be sacrificed and the loop bandwidth was increased until the needed settling time was achieved, while taking the suppression of the reference spurs into consideration. Capacitor multiplication was used to enable the integration of the loop filter (LF) on chip and the effect of the capacitor multiplier on the total PLL phase noise performance was quantified and evaluated. In addition, a very close matching between the measured and simulated phase noise of the system was achieved. The PLL consumes a power of 200 mW from 2 and 3 V supply voltages, while delivering a differential output power of −7 dBm, sufficient to drive the following I/Q modulator without additional amplification.

Keywords

PllHBTPhase noise60GHZ
Type
Research Papers
Information
International Journal of Microwave and Wireless Technologies , Volume 4 , Issue 4 , August 2012 , pp. 441 - 446
Copyright
Copyright © Cambridge University Press and the European Microwave Association 2012

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References

REFERENCES

[1]Winkler, W.; Borngräber, J.; Heinemann, B.; Herzel, F.: A fully integrated BiCMOS PLL for 60 GHz wireless applications in Proc. IEEE Int. Solid-State Circuits Conf., San Francisco, CA, USA, August 2005, 406–407.Google Scholar
[2]Cao, C.; Ding, Y.; Kenneth, K.: A 50-GHz phase-locked loop in 130-nm CMOS. IEEE J. Solid-State Circuits, 42 (8) (2007), 21–24.Google Scholar
[3]Hoshino, H.; Tachibana, R.; Mitomo, T.; Ono, N.; Yoshihara, Y.; Fujimoto, R.: A 60-GHz phase-locked loop with inductor-less prescaler in 90-nm CMOS in Proc. IEEE ESSCIRC Dig., Munich, Germany, 2007, 472–475.Google Scholar
[4]Lee, J.; Kim, H.; Yu, H.: A 52 GHz millimeter-wave PLL synthesizer for 60 GHz WPAN radio in Proc. IEEE Asian Solid-State Circuits Conf., Amsterdam, The Netherlands, 2008, 155–158.Google Scholar
[5]Kundert, K.: Predicting the Phase Noise and Jitter of PLL-Based Frequency Synthesizers. Available online at http://www.designers-guide.com.Google Scholar
[6]Rogers, J.; Plett, C.; Dai, F.: Integrated Circuit Design for High Speed Frequency Synthesis, 1st ed., Artech House, Norwood, MA, 2006.Google Scholar
[7]Barghouthi, A.; Ellinger, F.: Design of a 54 to 63 GHz differential common collector SiGe colpitts VCO in Proc. IEEE Conf. Microwave, Radar, and Wireless Communications, MIKON, Vilnius, Lithuania, 2010, 120–123.Google Scholar
[8]Lee, T.; Lee, H.; Hsiao, K.; Huang, Y.; Chen, G.: A 40-GHz distributed-load static frequency divider in Proc. IEEE Asian Solid-State Circuits Conf., Hsinchu, Taiwan, 2005, 205–208.Google Scholar
[9]Hwang, I.-C.: Area-efficient and self-biased capacitor multiplier for on-chip loop filter. IEE Electron. Lett., 42 (24), (2006), 1392–1393.CrossRefGoogle Scholar