A 60 GHz 14 dBm power amplifier with a transformer-based power combiner in 65 nm CMOS
Published online by Cambridge University Press: 08 April 2011
Abstract
A 52–61 GHz power amplifier (PA) is implemented in 65 nm bulk complementary metal oxide semiconductor (CMOS) technology. The proposed PA employs a transformer-based power combiner to sum the output power from two unit PAs. Each unit PA uses transformer-coupled two-stage differential cascode topology. The differential cascode PA is able to increase the output power and ensure stability. The transformer-based passives enable a compact layout with the PA core area of only 0.3 mm2. The PA achieves a peak power gain of 10.2 dB with 3-dB bandwidth of 9 GHz. The measured saturated output power is 14.8 dBm with a peak power-added efficiency (PAE) of 7.2%. The reverse isolation is smaller than −33 dB from 25 to 65 GHz. The PA consumes a quiescent current of 143 mA from a 1.6 V supply.
- Type
- Research Article
- Information
- International Journal of Microwave and Wireless Technologies , Volume 3 , Special Issue 2: 60 GHz Wireless Communication Circuits and Systems , April 2011 , pp. 99 - 105
- Copyright
- Copyright © Cambridge University Press and the European Microwave Association 2011
References
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