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20–25 Gbit/s low-power inductor-less single-chip optical receiver and transmitter frontend in 28 nm digital CMOS

Published online by Cambridge University Press:  02 May 2017

László Szilágyi ,
Guido Belfiore ,
Ronny Henker  and
Frank Ellinger
László Szilágyi*
Affiliation:
Technische Universität Dresden, Chair for Circuit Design and Network Theory, 01069 Dresden, Germany
Guido Belfiore
Affiliation:
Technische Universität Dresden, Chair for Circuit Design and Network Theory, 01069 Dresden, Germany
Ronny Henker
Affiliation:
Technische Universität Dresden, Chair for Circuit Design and Network Theory, 01069 Dresden, Germany
Frank Ellinger
Affiliation:
Technische Universität Dresden, Chair for Circuit Design and Network Theory, 01069 Dresden, Germany
*
Corresponding author: L. Szilágyi Email: [email protected]
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Abstract

The design of an analog frontend including a receiver amplifier (RX) and laser diode driver (LDD) for optical communication system is described. The RX consists of a transimpedance amplifier, a limiting amplifier, and an output buffer (BUF). An offset compensation and common-mode control circuit is designed using switched-capacitor technique to save chip area, provides continuous reduction of the offset in the RX. Active-peaking methods are used to enhance the bandwidth and gain. The very low gate-oxide breakdown voltage of transistors in deep sub-micron technologies is overcome in the LDD by implementing a topology which has the amplifier placed in a floating well. It comprises a level shifter, a pre-amplifier, and the driver stage. The single-chip frontend, fabricated in a 28 nm bulk-digital complementary metal–oxide–semiconductor (CMOS) process has a total active area of 0.003 mm2, is among the smallest optical frontends. Without the BUF, which consumes 8 mW from a separate supply, the RX power consumption is 21 mW, while the LDD consumes 32 mW. Small-signal gain and bandwidth are measured. A photo diode and laser diode are bonded to the chip on a test-printed circuit board. Electro-optical measurements show an error-free detection with a bit error rate of 10−12 at 20 Gbit/s of the RX at and a 25 Gbit/s transmission of the LDD.

Keywords

RF front-endsActive circuitsBroadband amplifiers
Type
Research Papers
Information
International Journal of Microwave and Wireless Technologies , Volume 9 , Special Issue 8: Biomedical Applications of RF/Microwave and Optics Technologies , October 2017 , pp. 1667 - 1677
Copyright
Copyright © Cambridge University Press and the European Microwave Association 2017 

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References

REFERENCES

[1]“The Zettabyte era – Trends and analysis,” in Cisco Visual Networking Index, Cisco White Paper, 2015.Google Scholar
[2]“Cisco global cloud index: Forecast and methodology, 2014–2019,” in Cisco White Paper, 2015.Google Scholar
[3] Okamoto, D. et al. : A 25-Gb/s 5 × 5 mm2 chip-scale silicon photonic receiver integrated with 28-nm CMOS transimpedance amplifier. IEEE J. Lightwave Technol., 34 (12) (2016), 2988–2995.CrossRefGoogle Scholar
[4] Takemoto, T.; Yamashita, H.; Yazaki, T.; Chujo, N.; Yong, L.; Matsuoka, Y.: A 25-to-28 Gb/s high-sensitivity (−9.7 dBm) 65 nm CMOS optical receiver for board-to-board interconnects. IEEE J. Solid State Circuits, 49 (10) (2014), 2259–2276.Google Scholar
[5] Toifl, T. et al. : A 3.1 mW/Gbps 30 Gbps quarter-rate triple-speculation 15-tap SC-DFE RX data path in 32 nm CMOS, in IEEE VLSI Circuits Symp., 2012, 102–103.Google Scholar
[6] Pan, Q. et al. : A 30-Gb/s 1.37-pJ/b CMOS receiver for optical interconnects. IEEE J. Lightwave Technol., 33 (4) (2015), 778–786.Google Scholar
[7] Schow, C.L. et al. : Low-power 16 × 10 Gb/s bi-directional single chip CMOS optical transceivers operating at ≪5 mW/Gb/s/link. IEEE J. Solid State Circuits, 44 (1) (2009), 301–313.Google Scholar
[8] Li, D. et al. : A Low-noise design technique for high-speed CMOS optical receivers. IEEE J. Solid State Circuits, 49 (6) (2014), 1437–1447.Google Scholar
[9] Chiang, P.-C.; Jiang, J.-Y.; Hung, H.-W.; Wu, C.-Y.; Chen, G.-S.; Lee, J.: 4 × 25 Gb/s transceiver with optical front-end for 100 GbE system in 65 nm CMOS technology. IEEE J. Solid State Circuits, 50 (2) (2015), 573–585.Google Scholar
[10] Huang, T.-C. et al. : A 28 Gb/s 1 pJ/b shared-inductor optical receiver with 56% chip-area reduction in 28 nm CMOS, in IEEE Int. Solid State Circuits Conf., 2014, 144–145.CrossRefGoogle Scholar
[11] Szilagyi, L.; Belfiore, G.; Henker, R.; Ellinger, F.: A high-voltage DC bias architecture implementation in a 17 Gbps low-power common-cathode VCSEL driver in 80 nm CMOS, in IEEE Int. Symp. Circuits and Systems, 2015, 2385–2388.CrossRefGoogle Scholar
[12] Rylyakov, A. et al. : A 25 Gb/s burst-mode receiver for low latency photonic switch networks. IEEE J. Solid State Circuits, 50 (12) (2015), 3120–3132.Google Scholar
[13] Xuan, Z.; Ding, R.; Liu, Y.; Baehr-Jones, T.; Hochberg, M.; Aflatouni, F.: A low-power 40 Gb/s optical receiver in silicon, in IEEE Radio Frequency Integrated Circuits, 2015, 315–318.Google Scholar
[14] Proesel, J.; Schow, C.; Rylyakov, A.: 25 Gb/s 3.6 pJ/b and 15 Gb/s 1.37 pJ/b VCSEL-based optical links in 90 nm CMOS, in IEEE Int. Solid State Circuits Conf., 2012, 418–419.CrossRefGoogle Scholar
[15] Pan, Q. et al. : A 41-mW 30-Gb/s CMOS optical receiver with digitally-tunable cascaded equalization, in Eur. Solid State Circuits Conf., 2014, 127–130.Google Scholar
[16] Han, J.; Yoo, K.; Lee, D.; Park, K.; Oh, W.; Park, S.M.: A low-power gigabit CMOS limiting amplifier using negative impedance compensation and its application. IEEE Trans. Very Large Scale Integr., 20 (3) (2012), 393–399.Google Scholar
[17] Kromer, C. et al. : A 100-mW 4 × 10 Gb/s transceiver in 80-nm CMOS for high-density optical interconnects. IEEE J. Solid State Circuits, 40 (12) (2005), 2667–2679.CrossRefGoogle Scholar
[18] Szilagyi, L.; Belfiore, G.; Henker, R.; Ellinger, F.: Area-efficient offset compensation and common-mode control circuit with switched-capacitor technique in an 18 Gbps optical receiver in 80 nm CMOS, in IEEE Optical Interconnects Conf., 2015, 58–59.Google Scholar
[19] Knochenhauer, C.; Wolf, R.; Sedighi, B.; Ellinger, F.: Fully integrated auto-zero feedback with lower cutoff frequency below 50 kHz in a 40 GBit/s transimpedance amplifier, in Semiconductor Conf. Dresden, 2011, 1–4.CrossRefGoogle Scholar
[20] Sedighi, B.; Scheytt, J.C.: 40 Gb/s VCSEL driver IC with a new output current and pre-emphasis adjustment method, in IEEE Microwave Theory and Technique Society, 2012, 1–3.Google Scholar
[21] Tsunoda, Y.; Sugawara, M.; Oku, H.; Ide, S.; Tanaka, K.: A 40 Gb/s VCSEL over-driving IC with group-delay-tunable pre-emphasis for optical interconnection, in IEEE Int. Solid State Circuits Conf., 2014, 154–155.Google Scholar
[22] Yazaki, T.; Chujo, N.; Yamashita, H.; Takemoto, T.; Yong, L.; Matsuoka, Y.: 25-Gbps × 4 optical transmitter with adjustable asymmetric pre-emphasis in 65-nm CMOS, in IEEE Int. Symp. Circuits and Systems, 2014, 2692–2695.Google Scholar
[23] Chujo, N. et al. : A 25 Gbps 65-nm CMOS low-power laser diode driver with mutually coupled peaking inductors for optical interconnects. IEEE Trans. Circuits Syst., 58 (9) (2011), 2061–2068.Google Scholar
[24] Chen, Y.; Gong, J.; Yao, J.; Tian, L.: 4-Channel 35 Gbit/s parallel CMOS LDD. IET Electron. Lett., 51 (15) (2015), 1178–1180.CrossRefGoogle Scholar
[25] Belfiore, G.; Szilagyi, L.; Henker, R.; Ellinger, F.: Common cathode VCSEL driver in 90 nm CMOS enabling 25 Gbit/s optical connection using 14 Gbit/s 850 nm VCSEL. IET Electron. Lett., 51 (4) (2015), 349–351.Google Scholar
[26] Saaedi, S.; Emami, A.: A 25 Gb/s 170 µW/Gb/s optical receiver in 28 nm CMOS for chip-to-chip optical communication, in IEEE Radio Frequency Integrated Circuits, 2014, 283–286.Google Scholar
[27] Awny, A. et al. : A 40 Gb/s Monolithically integrated linear photonic receiver in a 0.25 µm BiCMOS SiGe: C technology. IEEE Microw. Wireless Compon. Lett., 25 (7) (2015), 469–471.Google Scholar
[28] Schoeniger, D.; Henker, R.; Ellinger, F.: High-speed transimpedance amplifier with runtime adaptive bandwidth and power consumption in 0.13 µm SiGe BiCMOS. IET Electron. Lett., 52 (2) (2016), 154–156.Google Scholar
[29] Moeneclaey, B. et al. : A 40-Gb/s transimpedance amplifier for optical links. IEEE Photonic Technol. Lett., 27 (13) (2015), 1375–1378.Google Scholar
[30] Kuchta, D.M. et al. : A 71-Gb/s NRZ modulated 850-nm VCSEL-based optical link. IEEE Photonic Technol. Lett., 27 (6) (2015), 577–580.Google Scholar
[31] Rylyakov, A. et al. : 35-Gb/s VCSEL-based optical link using 32-nm SOI CMOS circuits, in IEEE Optical Fiber Communication Conf./National Fiber Optical Engineers Conf., 2013, 1–2.Google Scholar
[32] Soenen, W. et al. : 40 Gb/s PAM-4 transmitter IC for long-wavelength VCSEL links. IEEE Photonic Technol. Lett., 27 (4) (2015), 344–347.Google Scholar
[33] Kozlov, V.; Carusone, A.C.: A 15 Gb/s AC-coupled VCSEL driver with waveform shaping in 65 nm CMOS, in IEEE Compound Semiconductor Integrated Circuit Symp., 2015, 1–4.Google Scholar
[34] Wang, J. et al. : 4 × 30 Gbps 155 mW/channel VCSEL driver in 65 nm CMOS, in IEEE Optical Interconnects Conf., 2015, 111–112.Google Scholar
[35] Shibata, M.; Carusone, A. C.: A 26-Gb/s 1.80-pJ/b CMOS-driven transmitter for 850-nm common-cathode VCSELs, in IEEE Optical Fiber Communication Conf., 2015, 1–3.CrossRefGoogle Scholar