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A real-time on-chip network architecture for mixed criticality aerospace systems

Part of: The AJ Air Traffic Management Collection

Published online by Cambridge University Press:  13 August 2019

S. Majumder Open the ORCID record for S. Majumder [Opens in a new window] ,
J.F.D. Nielsen ,
A. La Cour-Harbo ,
H. Schiøler  and
T. Bak
S. Majumder*
Affiliation:
Department of Electronic Systems, Aalborg University Aalborg, Denmark
J.F.D. Nielsen*
Affiliation:
Department of Electronic Systems, Aalborg University Aalborg, Denmark
A. La Cour-Harbo*
Affiliation:
Department of Electronic Systems, Aalborg University Aalborg, Denmark
H. Schiøler*
Affiliation:
Department of Electronic Systems, Aalborg University Aalborg, Denmark
T. Bak*
Affiliation:
Department of Electronic Systems, Aalborg University Aalborg, Denmark
*
[email protected]
[email protected]
[email protected]
[email protected]
[email protected]
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Abstract

Integrated Modular Avionics enables applications of different criticality levels to share the same hardware platform with an established temporal and spatial isolation. On-chip communication systems for such platforms must support different bandwidth and latency requirements of applications while preserving time predictability. In this paper, our concern is a time-predictable on-chip network architecture for targeting applications in mixed-criticality aerospace systems. The proposed architecture introduces a mixed, priority-based and time-division-multiplexed arbitration scheme to accommodate different bandwidth and latency in the same network while preserving worst-case time predictability for end-to-end communication without packet loss. Furthermore, as isolation of erroneous transmission by a faulty application is a key aspect of contingency management, the communication system should support isolation mechanisms to prevent interference. For this reason, a sampling port and isolated sampling buffer-based approach is proposed with a transmission authorisation control mechanism, guaranteeing spatial and temporal isolation between communicating systems.

Keywords

Mixed-criticality systemNetwork on-chipReal-time systemEmbedded systemOn-Chip communicationIntegrated Modular Avionics
Type
Research Article
Information
The Aeronautical Journal , Volume 123 , Issue 1269 , November 2019 , pp. 1788 - 1806
Copyright
© Royal Aeronautical Society 2019 

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Footnotes

*

This research is funded by Independent Research Foundation Denmark under grant number 6111-00363B.

References

REFERENCES

FAA. Software Consideration in Airborne Systems and Equipment Certification, December 1992.Google Scholar
FAA. Assurance of Multicore Processors in Airborne Systems, DOT/FAA/TC-16/51, July 2017.Google Scholar
Alena, R. L., Ossenfort, J. P., Laws, K. I., Goforth, A. and Figueroa, F. Communications for integrated modular avionics, 2007 IEEE Aerospace Conference, 2007, pp 1–18. doi:10.1109/AERO.2007.352639.CrossRefGoogle Scholar
Hesham, S., Rettkowski, J., Göhringer, D. and Abd El Ghany, M. A. Survey on real-time network-on-chip architectures, International Symposium on Applied Reconfigurable Computing, 2015, pp 191–202.CrossRefGoogle Scholar
I. Radio Technical Commission for Aeronautics, RTCA: DO-297: Integrated Modular Avionics (IMA) Development Guidance and Certification Considerations, 2005.Google Scholar
Fuchs, C. M., Schneele, A. S. and Klein, E. The evolution of avionics networks from ARINC 429 to AFDX, Proceedings of the Seminars Future Internet (FI), Innovative Internet Technologies and Mobile Communication (IITM) and Aerospace Networks (AN), Technische University of Munich, Summer Semester 2012, pp 65–76.Google Scholar
Bieber, P., Boniol, F., Boyer, M., Noulard, E., Pagetti, C., Bieber, P., Boniol, F., Boyer, M., Noulard, E., Pagetti, C. and Challenges, N. New Challenges for Future Avionic Architectures, 2015, pp 1–10.Google Scholar
Perret, Q., Maurere, P., Noulard, E., Pagetti, C., Sainrat, P. and Triquet, B. Temporal isolation of hard real-time applications on many-core processors, 2016 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), 2016, pp 1–11. doi:10.1109/RTAS.2016.7461363.CrossRefGoogle Scholar
Moustapha Lo, F. M. P. R. and Valot, Nicolas. Implementing a real-time avionic application on a many-core processor, 42nd European Rotorcraft Forum (ERF), Lille, France, 2016, pp 1–10.Google Scholar
Majumder, S., Dalsgaard Nielsen, J., Bak, T. and La Cour-Harbo, A. Reliable flight control system architecture for agile airborne platforms: an asymmetric multiprocessing approach. The Aeronautical Journal, n.d., 1–23. doi:10.1017/aer.2019.30.CrossRefGoogle Scholar
Sano, K., Soudris, D., Hübner, M. and Diniz, P. C. Applied Reconfigurable Computing 11th International Symposium, ARC 2015 Bochum, Germany, April 13–17, 2015 Proceedings, Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), Vol. 9040, 2015, pp 191–201. doi:10.1007/978-3-319-16214-0.Google Scholar
Bertozzi, D. and Benini, L. Xpipes: a network-on-chip architecture for gigascale systems-on-chip, IEEE Circuits and Systems Magazine, 2004, 4, pp 18–31.CrossRefGoogle Scholar
Wiklund, D. and Liu, D. Socbus: switched network on chip for hard real time embedded systems, Proceedings International Parallel and Distributed Processing Symposium, 2003, p 8. doi:10.1109/IPDPS.2003.1213180.CrossRefGoogle Scholar
Pham, P. H., Park, J., Mau, P. and Kim, C. Design and implementation of backtracking wave-pipeline switch to support guaranteed throughput in network-on-chip, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2012, 20, (2), pp 270–283. doi:10.1109/TVLSI.2010.2096520.CrossRefGoogle Scholar
Wolkotte, P. T., Smit, G. J. M., Rauwerda, G. K. and Smit, L. T. An energy-efficient reconfigurable circuit-switched network-on-chip, 19th IEEE International Parallel and Distributed Processing Symposium, 2005, p. 155a. doi:10.1109/IPDPS.2005.95.CrossRefGoogle Scholar
Bolotin, E., Cidon, I., Ginosar, R. and Kolodny, A. QNOC: QOS architecture and design process for network on chip, Journal of Systems Architecture, 2004, 50, (2), pp 105–128, Special issue on networks on chip. doi:https://doi.org/10.1016/j.sysarc.2003.07.004.CrossRefGoogle Scholar
Lo, S. H., Lan, Y. C., Yeh, H. H., Tsai, W. C., Hu, Y. H. and Chen, S. J. QOS aware BINOC architecture, 2010 IEEE International Symposium on Parallel Distributed Processing (IPDPS), 2010, pp 1–10. doi:10.1109/IPDPS.2010.5470359.CrossRefGoogle Scholar
Corrêa, E. D. F., Silva, L. A. D. P. E., Wagner, F. R. and Carro, L. Fitting the router characteristics in NOCS to meet QOS requirements, Proceedings of the 20th Annual Conference on Integrated Circuits and Systems Design, SBCCI ’07, ACM, New York, NY, USA, 2007, pp 105–110. doi:10.1145/1284480.1284514.Google Scholar
Lu, C. H., Chiang, K. C. and Hsiung, P. A. Round-based priority arbitration for predictable and reconfigurable network-on-chip, 2009 International Conference on Field-Programmable Technology, 2009, pp 403–406. doi:10.1109/FPT.2009.5377690.CrossRefGoogle Scholar
Diemer, J., Ernst, R. and Kauschke, M. Efficient throughput-guarantees for latency-sensitive networks-on-chip, 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC), 2010, pp 529–534. doi:10.1109/ASPDAC.2010.5419828.CrossRefGoogle Scholar
Millberg, M., Nilsson, E., Thid, R. and Jantsch, A. “Guaranteed bandwidth using looped containers in temporally disjoint networks within the nostrum network on chip,” Proceedings Design, Automation and Test in Europe Conference and Exhibition, Paris, France, 2004, pp 890–895 Vol. 2. doi:10.1109/DATE.2004.1269001CrossRefGoogle Scholar
Goossens, K., Dielissen, J. and Radulescu, A. Aethereal network on chip: concepts, architectures, and implementations, IEEE Design Test of Computers, 2005, 22, (5), 414–421. doi:10.1109/MDT.2005.99.CrossRefGoogle Scholar
Goossens, K., Hansson, A. The aethereal network on chip after ten years: goals, evolution, lessons, and future, Design Automation Conference, 2010, pp 306–311. doi:10.1145/1837274.1837353.CrossRefGoogle Scholar
Stefan, R. A., Molnos, A. and Goossens, K. Daelite: a TDM NOC supporting QOS, multicast, and fast connection set-up, IEEE Transactions on Computers, 2014, 63, (3), pp 583–594. doi:10.1109/TC.2012.117.Google Scholar
Kasapaki, E., Schoeberl, M., Sorensen, R. B., Muller, C., Goossens, K. and Sparso, J. Argo: A Real-Time Network-on-Chip Architecture with an Efficient GALS Implementation, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2016, 24, (2), pp 479–492. doi:10.1109/TVLSI.2015.2405614.CrossRefGoogle Scholar