Preparation of high-quality polished sample surfaces is an essential step in the collection of microanalytical data on the microstructures of minerals and alloys. Poorly prepared samples can yield insufficient or inconsistent results and, in the case of gold, potentially no data due to the “beilby” layer. Currently, preparation of ore samples is difficult as they commonly contain both hard and soft mineral phases. The aim of our research is to produce suitably polished sample surfaces, on all phases, for electron backscatter diffraction analysis. A combination of chemical–mechanical polishing (CMP) and broad ion-beam polishing (BIBP) was used to tackle the problem. Our results show that it is critical to perform CMP first, as it produces a suitable polish on the hard mineral phases but tends to introduce more damage to the soft mineral surfaces. BIBP is essential to produce a high-quality polish to the soft phases (gold). This is a highly efficient method of sample preparation and is important as it allows the complete quantification of ore textures and all constituent mineral phases, including soft alloys.

Chemical–mechanical polishing, or planarization (CMP), has emerged as an increasingly important technology for integrated-circuit manufacturing. Consumables used during CMP interact in a complex manner with the polishing tool, the process conditions, and the wafer being polished. In this article, several advanced analytical methods are used to analyze the properties of slurries and pads under conditions similar to those found during CMP processing. Some of the key findings are that under these process conditions, pads can be stabilized with a heat treatment prior to installation on the polisher; pads absorb slurries at different rates, and slurries also react with the pads; and the mechanical properties of the pads are dependent on the orientation of the grooves on the pad. Dynamic rheometry was used to detect de-agglomeration in sheared slurries.

Chemical–mechanical polishing, or planarization (CMP), is one of several advanced microfabrication processes that provide complementary capabilities for constructing advanced electronic devices. At the current state of the art, CMP demonstrates significant advantages due to its high degree of process flexibility, particularly in the chemical formulation of polishing solutions and slurries. This article explores some possible future applications of CMP using new advanced materials other than silicon, silicon oxide, and silicon nitride. Such materials may include refractory and noble metals, high-κ insulators, and mixed metal oxide perovskites. Although no one can predict future applications with absolute certainty, it seems safe to conclude that CMP will remain a key microfabrication technology for the foreseeable future.

The primary aim of this issue of MRS Bulletin is to present an overview of the materials issues in chemical–mechanical planarization (CMP), also known as chemical–mechanial polishing, a process that is used in the semiconductor industry to isolate and connect individual transistors on a chip. The CMP process has been the fastest-growing semiconductor operation in the last decade, and its future growth is being fueled by the introduction of copper-based interconnects in advanced microprocessors and other devices. Articles in this issue range from providing a fundamental understanding of the CMP process to the latest advancements in the field. Topics covered in these articles include an overview of CMP, fundamental principles of slurry design, understanding wafer–pad–slurry interactions, process integration issues, the formulation of abrasive-free slurries for copper polishing, understanding surface topography issues in shallow trench isolation, and emerging applications.

The formulation of slurries for chemical–mechanical planarization (CMP) is currently considered more of an art than a science, due to the lack of understanding of the wafer, slurry, and pad interactions involved. Several factors, including the large number of input variables for slurries and the synergistic interplay among input variables and output parameters, further complicate our ability to understand CMP phenomena. This article provides a fundamental basis for the choice of chemical additives and particles needed for present-day and next-generation slurry design. The effect of these components on nanoscale and microscale interaction phenomena is investigated. Methodologies are suggested for the development of next-generation slurries required to overcome CMP challenges related to defectivity and the surface topography of soft materials such as Low-κ dielectrics and copper.

As the minimum feature size of microelectronic devices shrinks down to 130 nm, copper has been successfully adopted into logic applications.1–3 Copper requires damascene processing, which involves etching features into a dielectric substrate, filling the features with metal, and removing any excess metal. Therefore, chemical—mechanical planarization (CMP) is a key process in the final definition of the inlaid copper wires on a circuit. A second advance in the back-end processing of copper is the changing of the dielectric from SiO2 to a Low-κ material, which allows a thicker layer of dielectric to be used. Low-k dielectric films have much lower mechanical properties than SiO2; consequently, this poses new challenges in developing integration schemes.1,3–8

An abrasive-free polishing (AFP) solution for chemical–mechanical planarization (CMP) of copper films on semiconductor wafers has been developed to overcome such disadvantages of conventional CMP as dishing, erosion, Cu and oxide loss, and microscratching. Electrochemical methods are an effective way of understanding the role of each chemical component in the AFP solution in order to optimize its performance. Analysis of the reaction layer of Cu elucidates the reasons for the excellent results that have been obtained. By applying the AFP solution for Cu CMP in combination with a slurry for CMP of the metal barrier layer, seven-level multilayer Cu interconnections can be successfully fabricated.

As advancing technologies increase the demand for planarity in integrated circuits, nanotopography has emerged as an important concern in shallow trench isolation (STI) on wafers polished by means of chemical–mechanical planarization (CMP). Previous work has shown that nanotopography—small surface-height variations of 10–100 nm in amplitude extending across millimeter-scale lateral distances on virgin wafers—can result in CMP-induced localized thinning of surface films such as the oxides or nitrides used in STI. A contact-wear CMP model can be employed to produce maps of regions on a given starting wafer that are prone to particular STI failures, such as the lack of complete clearing of the oxide in low spots and excessive erosion of nitride layers in high spots on the wafer. Stiffer CMP pads result in increased nitride thinning. A chip-scale pattern-dependent CMP simulation shows that substantial additional dishing and erosion occur because of the overpolishing time required due to nanotopography. Projections indicate that nanotopography height specifications will likely need to decrease in order to scale with smaller feature sizes in future IC technologies.