Six four-element balun topologies are introduced that enable complex impedance matching in addition to common-mode rejection. Design equations for these topologies are presented. Three of these networks are universal, while the other three are capable of performing only specific impedance transformations. Examples of these networks were designed and fabricated along with a traditional lattice balun network for an operating frequency of 300 MHz. These networks were verified through extensive electromagnetic simulations and by measuring the fabricated networks. The fabricated novel network examples were able to achieve common-mode rejection ratios above 20 dB, power wave reflection coefficients below −20 dB, and insertion losses of approximately 0.1 dB; these results were similar to or better than the performance of the fabricated traditional lattice balun. The design example networks also provided power matching and low insertion loss over a greater bandwidth compared to the fabricated traditional network. These networks will allow for the footprints of lumped-element balun circuitry to be reduced, which is particularly useful in integrated circuit design. These topologies are also expected to further increase radio-frequency (RF) circuit design flexibility by offering more alternative realizations.

This manuscript presents a millimeter-wave GaN high-power amplifier (HPA) intended for next generation inter-satellite links (ISLs). The proposed architecture achieves a fractional bandwidth wider than 18% in the V-band spectrum, to deliver a 10 Gbit/s throughput compatible with multi-thousand-km ISLs. Core of the HPA is the monolithic microwave integrated circuits (MMIC ) power amplifier which covers the whole 59–71 GHz band with high efficiency through innovative topologies and a cutting-edge gallium nitride on silicon carbide (GaN-on-SiC) process. The MMIC is then parallelized by means of a 1-to-8 splitter/combiner to obtain a V-band 10 W GaN HPA. Measurement results show a peak small-signal gain of 25.6 dB, 6.5% peak power-added efficiency, and a maximum P1dB of 40.3 dBm.

Full duplex (FD) could potentially double wireless communications capacity by allowing simultaneous transmission and reception on the same frequency channel. A single antenna architecture is proposed here based on a modified rat-race coupler to couple the transmit and receive paths to the antenna while providing a degree of isolation. To allow the self-interference cancellation (SiC) to be maximized, the rat-race coupler was made tuneable. This compensated for both the limited isolation of the rat race and self-interference caused by antenna mismatch. Tuneable operation was achieved by removing the fourth port of the rat race and inserting a variable attenuator and variable phase shifter into the loop. In simulation with a 50 Ω load on the antenna port, better than −65 dB narrowband SiC was achieved over the whole 2.45 GHz industrial, scientific and medical (ISM) band. Inserting the S-parameters of a commercially available sleeve dipole antenna into the simulation, better than −57 dB narrowband SiC could be tuned over the whole band. Practically, better than −58 dB narrowband tuneable SiC was achieved with a practical antenna. When excited with a 20 MHz Wi-Fi signal, −42 dB average SiC could be achieved with the antenna.

In recent years, millimeter wave (MMW) has received tremendous interest among researchers, which offers systems with high data rate communication, portability, and finer resolution. The design of the antenna at MMWs is challenging as it suffers from fabrication and measurement complexities due to associated smaller dimensions. Current state-of-the-art MMW dual-band antenna techniques demand high precision fabrication, which increases the overall cost of the system. Henceforth, the design of an MMW antenna with fabrication and measurement simplicity is quite challenging. In this paper, a simple coplanar waveguide (CPW) fed single-band MMW antenna operating at 94 GHz (W band) and a dual-band MMW antenna operating concurrently at 60 GHz (V band) and 86 GHz (E band) have been designed, fabricated, and measured. A 50 Ω CPW-to-microstrip transition has also been designed to facilitate probe measurement compatibility and to provide proper feeding to the antenna. The fabricated single frequency 94 GHz antenna shows a fractional bandwidth of 11.2% and E-plane (H-plane) gain 6.17 dBi (6.2 dBi). Furthermore, the designed MMW dual-band antenna shows fractional bandwidth: 2/6.4%, and E-plane (H-plane) gain: 7.29 dBi (7.36 dBi)/8.73 dBi (8.68 dBi) at 60/86 GHz, respectively. The proposed antenna provides a simple and cost-effective solution for different MMW applications.

A multi-octave receiver chain is presented for the use in a monolithic integrated vector network analyzer. The receiver exhibits a very wide frequency range of 1–32 GHz, where the gain meets the 3 dB-criterion. The differential receiver consists of an ultra-wideband low noise amplifier, an active mixer and an output buffer and exhibits a maximum conversion gain (CG) of 16.6 dB. The main design goal is a very flat CG over five octaves, which eases calibration of the monolithic integrated vector network analyzer. To realize variable gain functionality, without losing much input matching, an extended gain control circuit with additional feedback branch is shown. For the maximum gain level, a matching better than −10 dB is achieved between 1–28 GHz, and up to 30.5 GHz the matching is better than −8.4 dB. For both, the input matching and the gain of the LNA, the influence of the fabrication tolerances are investigated. A second gain control is implemented to improve isolation. The measured isolations between RF-to-LO and LO-to-RF are better than 30 dB and 60 dB, respectively. The LO-to-IF isolation is better than 35 dB. The noise figure of the broadband receiver is between 4.6 and 5.8 dB for 4–32 GHz and the output referred 1-dB-compression-point varies from 0.1 to 4.3 dBm from 2–32 GHz. The receiver draws a current of max. 66 mA at 3.3 V.

The contribution of this paper is to propose a novel rat-race hybrid coupler of arbitrary coupling coefficient. Traditionally, the rat-race hybrid couplers are built by various loop-alike transmission-lines of multiple quarter-wavelength, and in this paper, we approach the coupler design by using a circular substrate integrated waveguide (SIW) cavity (SIWC). The employed SIWC supports two mutually orthogonal degenerate modes, and cavity field is formed by the two modes in an arbitrary weighting ratio which defines the proposed rat-race coupler's coupling coefficient. The cavity is excited by a microstrip combined coupling slot with the microstrip along a specifically chosen direction. The energy of each degenerate mode can be solely extracted by an associated subminiature version A (SMA) whose position is carefully determined. The isolation between the coupling slots is assured by their perpendicular layout, and the isolation between the SMA probes is obtained by the orthogonality of the two degenerate modes. Experiments are conducted on the 3- and 10-dB coupling coefficient samples to verify this novel rat-race coupler design. The measurements agree well with the simulations, and circuit's good performance is observed in terms of coupling precision, isolations, and small phase imbalances.

This paper presents a fully-integrated direct-conversion fundamentally-operated mixer-first quadrature receiver module with a tunable LO in the 219–266 GHz band. It has been implemented in a 0.13-μm SiGe heterojunction bipolar transistor technology. It includes an on-chip LO path driven externally from the printed circuit board (PCB) connector level at 13.6–16.7 GHz. A hybrid coupler generates the quadrature LO signal, which drives a pair of double-balanced fundamentally-operated down-conversion mixers, whose RF ports are connected to a wideband lens-integrated on-chip ring antenna. The chip-on-lens assembly is placed in the recess of a high-speed PCB and wire-bonded. To compensate the inductive behavior of the wire-bond interconnection between the chip and the PCB at the high-speed IF outputs, an on-board 8-section step-impedance low-pass filter has been implemented. The module shows a 47 GHz 3-dB radio frequency/local oscillator operation bandwidth (BW), a peak conversion gain of 7.8 dB, a single-side-band noise figure of 11.3 dB, and a 3-dB IF BW of 13 GHz. The in-phase and quadrature amplitude imbalance stays below 1.58 dB for the 210–280 GHz band. The down-conversion and the baseband stages consume together 75.5 mW, while the LO path 378 mW. The maximum data-rate achieved with this receiver in combination with the transmitter presented in [1–3] is 60 Gbps for quadrature phase shift keying modulation.

This paper presents the design and characterization of a D-band (110–170 GHz) monolithic microwave integrated direct carrier quadrature modulator and demodulator circuits with on-chip quadrature local oscillator (LO) phase shifter and radio frequency (RF) balun fabricated in a 130 nm SiGe BiCMOS process with ft/fmax of 250 GHz/400 GHz. These circuits are suitable for low-power ultra-high-speed wireless communication and can be used in both homodyne and heterodyne architectures. In single-sideband operation, the modulator demonstrates a maximum conversion gain of 9.8 dB with 3-dB RF bandwidth of 33 GHz (from 119 GHz to 152 GHz). The measured image rejection ratio (IRR) and LO suppression are 19 dB and 31 dB, respectively. The output P1dB is −4 dBm at 140 GHz RF and 1 GHz intermediate frequency (IF) and the chip consumes 53 mW dc power. The demodulator, characterized as an image reject mixer, exhibits 10 dB conversion gain with 23-dB IRR. The measured 3-dB RF bandwidth is 36 GHz and the IF bandwidth is 18 GHz. The active area of both the chips is 620 µm × 480 µm including the RF and LO baluns. A 12-Gbit/s QPSK data transmission using 131-GHz carrier signal is demonstrated on modulator with measured modulator-to-receiver error vector magnitude of 21%.

An integrated reconfigurable antenna capable of spectrum sensing along with various reconfiguration features such as polarization, frequency, bandwidth, and radiation pattern is proposed here. The proposed antenna senses the spectrum by UWB antenna from 2 to 11 GHz to identify the spectrum conditions. After identifying the direction of maximum traffic or interference, the proposed antenna accordingly reconfigures its radiation pattern in order to mitigate the interference using switchable shorting posts. The antenna can reconfigure its polarization state using a switchable slot in the circular antenna. Frequency reconfigurability is obtained by using a varactor diode from 2 to 4 GHz. The antenna can reconfigure its bandwidth from UWB to NB by switching the active ports state. Measured and simulated results of the proposed antenna shows very good agreement, hence, validating the proposed design.

This paper proposes a unique, first of its kind fabrication technique for the making of textile antennas. A novel method that provides scope for automation in textile antenna production is presented here. A completely integrated textile antenna fabrication method that eliminates the tasks of positioning and fastening of the various components of a patch antenna is discussed. The technique employs multilayer weaving for the production of a wearable antenna on a cotton substrate. Silver yarn is used for the conductive regions of the textile antenna. Two layers of woven cotton serve to isolate the radiating patch from the ground plane of the antenna. The designed antenna was chosen to operate at the frequency of 2.45 GHz for Wireless Local Area Network. The built prototype resonated at 2.43 GHz with a |S11|of −18.62 dB. The integrated textile antenna exhibited a gain of 1.06 dBi at 2.43 GHz.

Design guidelines for fractional-N phase-locked loops with a high spectral purity of the output signal are presented. Various causes for phase noise and spurious tones (spurs) in integer-N and fractional-N phase-locked loops (PLLs) are briefly described. These mechanisms include device noise, quantization noise folding, and noise coupling from charge pump (CP) and reference input buffer to the voltage-controlled oscillator (VCO) and vice versa through substrate and bondwires. Remedies are derived to mitigate the problems by using proper PLL parameters and a careful chip layout. They include a large CP current, sufficiently large transistors in the reference input buffer, linearization of the phase detector, a high speed of the programmable frequency divider, and minimization of the cross-coupling between the VCO and the other building blocks. Examples are given based on experimental PLLs in SiGe BiCMOS technologies for space communication and wireless base stations.

The paper presents a two-dimensional (2D) extended envelope memory polynomial model for concurrent dual-band radio frequency (RF) power amplifiers (PAs). The model is derived based on the physical knowledge of a dual-band RF PA. The derived model contains cross-modulation terms not included in previously published models; these terms are found to be of importance for both behavioral modeling and digital predistortion (DPD). The performance of the derived model is evaluated both as the behavioral model and DPD, and the performance is compared with state-of-the-art 2D-DPD and dual-band generalized memory polynomial (DB-GMP) models. Experimental result shows that the proposed model resulted in normalized mean square error of −51.7/−51.6 dB and adjacent channel error power ratio of −63.1/−63.4 dB, for channel 1/2, whereas the 2D-DPD resulted in the largest model error and DB-GMP resulted in model parameters that are three times more than those resulted with the proposed model with the same performance. As pre-distorter, the proposed model resulted in adjacent channel power ratio of −55.8/−54.6 dB for channel 1/2 and is 7–10 dB lower than those resulted with the 2D-DPD model and 2–4 dB lower compared with the DB-GMP model.

The design of an analog frontend including a receiver amplifier (RX) and laser diode driver (LDD) for optical communication system is described. The RX consists of a transimpedance amplifier, a limiting amplifier, and an output buffer (BUF). An offset compensation and common-mode control circuit is designed using switched-capacitor technique to save chip area, provides continuous reduction of the offset in the RX. Active-peaking methods are used to enhance the bandwidth and gain. The very low gate-oxide breakdown voltage of transistors in deep sub-micron technologies is overcome in the LDD by implementing a topology which has the amplifier placed in a floating well. It comprises a level shifter, a pre-amplifier, and the driver stage. The single-chip frontend, fabricated in a 28 nm bulk-digital complementary metal–oxide–semiconductor (CMOS) process has a total active area of 0.003 mm2, is among the smallest optical frontends. Without the BUF, which consumes 8 mW from a separate supply, the RX power consumption is 21 mW, while the LDD consumes 32 mW. Small-signal gain and bandwidth are measured. A photo diode and laser diode are bonded to the chip on a test-printed circuit board. Electro-optical measurements show an error-free detection with a bit error rate of 10−12 at 20 Gbit/s of the RX at and a 25 Gbit/s transmission of the LDD.

With the increasing demand of millimeter-wave (MMW) communication, the performance of its frequency synthesizer has high requirements. In this paper, a multiple conversion mechanism, which used hybrid frequency synthesis technique is presented. Some key modules include linear frequency-modulated generator, agile, and low phase noise local oscillators (LOs), automatic gain control, receiver front-end circuit, and MMW LO circuits are discussed and simulated to verify correctness of the mechanism. The experimental results show that, spurious is better than −65 dBc, phase noise is no more than −80 dBc/Hz@1 kHz, and the maximum frequency-hopping time is <1.8 µs.