Worldwide adoption of 5G mobile devices has been one of the main driving engines behind semiconductor industry. Since the initial release in 2020, 5G-enabled devices have surpassed the market penetration of 3G/4G smartphones. 5G brings higher data capacity, low latency, and new applications. These are possible due to lower feature nodes such as FinFET 3 nm/5 nm but also due to improvements of the 5G radio frequency (RF)front-end circuitry. This paper presents 5G RF front-end architectures with novel circuits and measurement details which will be part of future 5G advanced and 6G mobile devices and are easier to be controlled using digital circuitry. The paper presents an envelope-controlled power amplifier (PA) principle, along with a novel simplified calibration architecture designed for 5G/5G+ operating under 6 GHz, as well as for frequency range 2 millimeter-wave PAs. An earlier version of this paper was presented at the 2023 53rd European Microwave Conference and was published in the Proceedings [Balteanu F, Thoomu K, Pingale A, Venimadhavan S, Sarkar S, Choi Y, Modi H, Drogi S, Lee J and Agarwal B (2023) Enabling RF circuit techniques for 5G and beyond In 53rd European Microwave Conference (EuMC), Berlin, Germany, 22–25].

Worldwide adoption of fourth-generation wireless (4G) long-term evolution (LTE) smartphones and the actual transition to fifth-generation wireless(5G) is the main driving engine for semiconductor industry. 5G is expected to reach high data rate speeds (1 Gbps) and low latency (<1 ms). 5G requires more RF bandwidth and therefore an increase in the number of components such as RF switches, acoustic filters, and power amplifiers integrated in few RF front-end modules. Also, there is an increase in the number of RF radio transmitters and receivers operating at the same time. This paper presents new architecture elements for 5G RF front-end modules. Circuit details and measurements are presented to reduce the RF noise, improve the efficiency, and help the coexistence of multiple radio transmitters. These circuits will help extend the 5G applications with radar-like sensing applications, remote medicine, and autonomous driving.

A radio frequency (RF) 3-bit digital power amplifier (DPA) is described in this paper. It consists of three RF amplifiers connected at their outputs with a transmission line (TL) network. The three amplifiers are designed for different output powers (POUT). The TL network allows them to load-pull one other to achieve eight different amplitude states by alternatively enabling and disabling the amplifiers via their gate bias. A prototype was designed in the National Instruments' Microwave Office (MWO) for 500 MHz with the aid of a genetic algorithm to optimize the TL network for all seven active (on-) states. The optimizer efficiencies goals were based on data derived from load-pull simulation. The POUT goals were based on a 1 Vrms step-size. In simulation, ≥50% efficiency was achieved at all on-states with 29.7 dBm peak POUT. A practical prototype based on the simulation achieved an efficiency of ≥40% over all seven on-states. A peak POUT of 28.9 dBm was achieved, with the lowest state at 22.4 dBm.

In this paper, the concept of load-modulated power amplifiers (PAs) is studied. Two GaN-HEMT power amplifiers (PAs), targeted for high efficiency at maximum and output back-off (OBO) power levels, are designed, implemented, and tested across 1.8–2.2 GHz. The load modulation in the first design is realized by tuning the shunt capacitors in the output matching network. A novel method is employed in the second design, where barium–stronrium–titante is used for the realization of load modulation. The large-signal measurement results across the desired band show 59–70% drain efficiency at 44–44.5 dBm output power for both designs. Using the available tunable technique, the drain efficiency of the PAs is enhanced by 4–20% at 6 dB OBO across the bandwidth.